- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16HCT9VJE8 Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | CR16HCT9VJE8 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 53/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT9VJE8 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)當(dāng)前第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
53
www.national.com
Timer/Counter I (TnCNT1) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRA
register and counting proceeds down from the reloaded val-
ue. In addition, the TnA pin is toggled on each underflow if
this function is enabled by the TnAEN bit. The initial state of
the TnA pin is software-programmable. When the TnA pin is
toggled from low to high, it sets the TnCPND interrupt pend-
ing flag and also generates an interrupt if the interrupt is en-
abled by the TnAIEN bit.
Because TnA toggles on every underflow, a 50% duty cycle
PWM signal can be generated on TnA without any further ac-
tion from the CPU once the pulse train is initiated.
Timer/Counter II (TnCNT2) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRB
register and counting proceeds down from the reloaded val-
ue. In addition, each underflow sets the TnDPND interrupt
pending flag and generates an interrupt if the interrupt is en-
abled by the TnDIEN bit.
15.2.4
Mode 4 is the Single Input Capture and Single Timer mode,
which provides one external event counter and one system
timer.
Figure 17 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 4. This mode offers a combination
of Mode 3 and Mode 2 functions. Timer/Counter I is used as
a system timer as in Mode 3 and Timer/Counter II is used as
a capture timer as in Mode 2, but with a single input rather
than two inputs.
Mode 4: Input Capture Plus Timer
Timer/Counter I (TnCNT1) operates the same as in Mode 3.
It counts down at the rate of the selected clock. Upon under-
flow, it is reloaded from the TnCRA register and counting pro-
ceeds down from the reloaded value. The TnA pin is toggled
on each underflow if this function is enabled by the TnAEN
bit. When the TnA pin is toggled from low to high, it sets the
TnCPND interrupt pending flag and also generates an inter-
rupt if the interrupt is enabled by the TnAIEN bit. A 50% duty
cycle PWM signal can be generated on TnA without any fur-
ther action from the CPU once the pulse train is initiated.
Timer/Counter II (TnCNT1) counts down at the rate of the se-
lected clock. The TnB pin functions as the capture input. A
transition received on TnB transfers the timer contents to the
TnCRB register. The input pin can be configured to sense ei-
ther rising or falling edges.
The TnB input can be configured to preset the counter to
FFFF hex upon reception of a valid capture event. In this
case, the current value of the counter is transferred to the
capture register and then the counter is preset to FFFF hex.
The values captured in the TnCRB register at different times
reflect the elapsed time between transitions on the TnA pin.
The input signal on TnB must have a pulse width equal to or
greater than one system clock cycle.
There are two separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending flag. The
two interrupt events are reception of a transition on TnB and
underflow of the TnCNT2 counter. The enable bits for these
events are TnBIEN and TnDIEN, respectively.
Neither Timer/Counter I (TnCNT1) nor Timer/Counter II
(TnCNT2) can be configured to operate as an external event
Figure 16.
Mode 3: Dual Independent Timer/Counter Block Diagram
Reload A
TnCRA
Timer/Counter I
TnCNT1
Reload B
TnCRB
Timer I
Clock
TnA
TnAIEN
TnAPND
TnDIEN
TnDPND
Timer
Interrupt I
Timer
Interrupt II
TnAEN
Timer/Counter II
TnCNT2
Timer II
Clock
TnB
Clock
Selector
Underflow
Underflow
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCT9VJE8Y | Microcontroller |
| CR16HCT9VJE9 | Microcontroller |
| CR16HCT9VJE9Y | Microcontroller |
| CR16MCT5VJE8Y | Microcontroller |
| CR16MCT5VJE9Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCT9VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJEX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。