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| 型號(hào)： | CR16HCT9VJE7 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 119/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT9VJE7 |
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119
www.national.com
22.0
A/D Converter
The A/D Converter (ADC) module is a 12-channel, multi-
plexed-input, analog-to-digital converter. The A/D Converter
receives an analog voltage on an input pin and converts that
voltage into an 8-bit digital value using successive approxi-
mation. The CPU can then read the result from a memory-
mapped register. The module supports four automated oper-
ating modes, providing single-channel or 4-channel scanned
operation in single-conversion or continuous mode.
Figure 74 is a block diagram of the A/D Converter module.
The analog input signal is selected from the analog inputs us-
ing a 12-channel analog multiplexer. The input pins are alter-
nate functions of Port I.
A sample-and-hold circuit samples the analog voltage prior
to conversion and holds it stable throughout the conversion
process. A programmable initial delay period allows the sam-
pled voltage to stabilize before the conversion process be-
gins.
The input voltage range is from 0V to V
REF
(the A/D refer-
ence voltage). The device has a separate pin, V
REF
, for the
reference voltage.
A capacitor should be connected between the V
REF
and the
A
VCC
pin in order to minimize noise. The recommended val-
ue for this capacitor is about 0.47mF.
The internal analog-to-digital converter block is based on a
successive approximation algorithm, which compares the
sampled voltage against an internally generated sequence of
analog voltages. The result is a linear conversion of the ana-
log voltage to an unsigned 8-bit value ranging from 00 hex for
0.0 volts to FF hex for V
REF
.
The clock used by the converter block is generated by a clock
divider that scales down the system clock by a programma-
ble factor. The conversion algorithm requires ten A/D Con-
verter clock cycles, or 10 microseconds at the maximum
allowed A/D Converter clock rate of 2 MHz.
Conversion can start after the power supply is stable and AD-
CEN set for 30 ms.
The conversion results are stored in a 4-level data buffer. De-
pending on the operating mode, the buffer can hold the re-
sults of four successive conversions from a single channel or
four conversions from adjacent channels scanned in se-
quence.
22.1
The A/D Converter can be configured to operate in any one
of four modes:
— Single channel, single conversion
— Single channel, continuous conversion
— 4-channel scan, single conversion
— 4-channel scan, continuous conversion
The configuration is set by the SCAN and CONT fields in the
ADC Control 2 Register (ADCCNT2), as indicated in
OPERATING MODES
Table 41. The A/D converter must be disabled when switch-
ing to a different mode.
Table 41
ADC Operation Modes
22.1.1
In the single channel, single conversion mode, the A/D Con-
verter performs a single conversion using a specified chan-
nel.
The software starts a conversion by setting the START bit in
the ADCCNT2 register. Upon completion of the conversion,
the A/D Converter places the result in register ADDATA0,
clears the START bit, and sets the EOC (end of conversion)
bit in the ADCST register. If the A/D Converter interrupt is en-
abled, an interrupt to the CPU is generated at this time.
Single Channel, Single Conversion Mode
22.1.2
In the single channel, continuous conversion mode, the A/D
Converter performs conversions repeatedly using the same
specified channel.
The software starts a conversion sequence by setting the
START bit. The A/D Converter performs four A/D conver-
sions in sequence using the same channel, pausing only for
the programmable sampling delay time used in all conver-
sion operations. It loads the four results into the A/D data reg-
isters in sequence, starting with ADDATA0 and ending with
ADDATA3. After it loads all four registers, it sets the EOC
(end of conversion) bit. If the A/D Converter interrupt is en-
abled, an interrupt to the CPU is generated at this time.
The START bit remains set until cleared by the software. If
the software does not clear the START bit, the A/D Converter
continues performing conversions using the same input
channel, storing the results in ADDATA0 following ADDATA3.
To prevent an overrun error, the software must read the re-
sults from the data registers before the A/D Converter writes
the next result into ADDATA0 following ADDATA3.
When the software clears the START bit, the A/D Converter
first completes the conversion currently in progress, then
stops and sets the EOC bit. A 2-bit buffer pointer in the
ADCST register points to the register containing the final re-
sult.
Single Channel, Continuous Conversion Mode
22.1.3
In the 4-channel scan, single conversion mode, the A/D Con-
verter performs four conversions using four adjacent input
channels.
The software starts the conversion sequence by setting the
START bit. The A/D Converter performs four A/D conver-
sions in sequence using four adjacent channels, starting with
the specified channel and pausing only for the programmable
sampling delay time. It loads the four results into the A/D data
registers in sequence, starting with ADDATA0 and ending
4-Channel Scan, Single Conversion Mode
SCAN CONT
Mode
00
00
01
01
0
1
0
1
Single Channel, Single Conversion
Single Channel, Continuous Conversion
4 Channels Scan, Single Conversion
4 Channel Scan, Continuous Conversion
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相關(guān)代理商/技術(shù)參數(shù) |
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| CR16HCT9VJE7Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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