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| 型號(hào)： | CR16HCT9 |
| 文件頁(yè)數(shù)： | 70/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT9 |
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70
MSKM
MICROWIRE Clocking Mode. When cleared to
0, the device uses the normal clocking mode.
When set to 1, the device uses the alternate
clocking mode. In the normal mode, the output
data is clocked out on the falling edge of MSK
and the input data is sampled on the rising
edge of MSK. In the alternate mode, the output
data is clocked out on the rising edge of MSK
and the input data is sampled on the falling
edge of MSK.
MICROWIRE Idle. This bit sets the value of the
MSK output when the MICROWIRE interface is
idle: 0 for low or 1 for high. This bit should be
changed only when the MICROWIRE interface
module is disabled (MEN=0) or when no bus
transaction is in progress (MWSTAT.MBSY=0).
MICROWIRE Clock Divider Value. This 7-bit
field specifies the divide-by factor used for gen-
erating the MSK shift clock from the system
clock. The divide-by factor is 2*(MCDV[6:0]+1).
This allows selection of a divide-by ratio from 2
to 256. This field is ignored in slave mode
(MWCTL1.MMNS=0).
MIDL
MCDV
17.5.3
The MICROWIRE Status Register is a word-wide, read-only
register that shows the current status of the MICROWIRE in-
terface module. Upon reset, all non-reserved bits are cleared
to 0. The register format is shown below.
15
3
Reserved
MOVR
MICROWIRE Status Register (MWSTAT)
MBSY
MICROWIRE Busy. This bit, when set to 1, in-
dicates that the MICROWIRE shifter is busy.
In master mode, MBSY is set to 1 when the
MWDAT register is written. In slave mode, this
bit is set to 1 on the first leading edge of MSK
when MCS is asserted or when the MWDAT
register is written, whatever occurs first.
In both master and slave modes, this bit is
cleared to 0 when the MICROWIRE data trans-
fer sequence is completed and the read buffer
is ready to receive the new data; in other
words, when the previous data held in the read
buffer has already been read.
If the previous data in the read buffer has not
been read and a new data has been received
into the shift register, the MBSY will not be
cleared, as the transfer could not be complet-
ed. This is because the contents of the shift
register could not be copied into the read buff-
er.
MICROWIRE Read Buffer Full. This bit, when
set to 1, indicates that the MICROWIRE read
buffer is full and ready to be read by the soft-
ware. It is set to 1 when the shifter loads the
read buffer, which occurs upon completion of a
transfer sequence if the read buffer is empty.
MRBF
The MRBF bit is updated when the MWDAT
register is read. At that time, the MRBF bit is
cleared to 0 if the shifter does not contain any
new data (in other words, the shifter is not re-
ceiving data or has not yet received a full byte
of data). The MRBF bit remains set to 1 if the
shifter already holds new data at the time that
MWDAT is read. In that case, MWDAT is imme-
diately reloaded with the new data and is ready
to be read by the software.
MICROWIRE Receive Overrun Error. This bit,
when set to 1 in master mode, indicates that a
receive overrun error has occurred. This error
occurs when the read buffer is full, the 8-bit
shifter is full, and a new data transfer sequence
starts. This bit is undefined in slave mode.
The MOVR bit, once set, remains set until
cleared by the software. The software clears
this bit by writing a 1 to its bit position. Writing
a 0 to this bit position has no effect. No other
bits in the MWSTAT register are affected by a
write operation to the register.
MOVR
2
1
0
MRBF
MBSY
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