The power-fail (VDD Monitor) r" />
參數(shù)資料
型號(hào): CP2201EK
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 46/108頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL FOR CP2201 ETH CTRLR
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)傳感器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CP2200,CP2201
主要屬性: 溫度和光傳感器
次要屬性: 圖形用戶界面
已供物品: 板,電源,線纜,CD
產(chǎn)品目錄頁(yè)面: 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN
336-1312-ND - IC ETH CTRLR SNGL-CHIP 48TQFP
其它名稱: 336-1316
CP2200/1
42
Rev. 1.0
9.7. De-Selecting Interrupt Sources
The power-fail (VDD Monitor) reset is automatically enabled after every power-on reset. The software reset is
enabled after every device reset, regardless of the reset source. The RSTEN register can be used to prevent either
of these two reset sources from generating a device reset.
Register 14. RSTEN: Reset Enable Register
Table 13. Reset Electrical Characteristics
VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
Min
Typ
Max
UNITS
RST Output Low Voltage
IOL = 8.5 mA
0.6
V
RST Input High Voltage
0.7 x VDD
——
V
RST Input Low Voltage
0.3 x VDD
V
RST Input Pullup Current
25
50
A
VDD POR Threshold (VRST)
2.2
2.4
2.6
V
Minimum /RST Low Time to
Generate a System Reset
15
s
VDD Monitor Turn-on Time
100
s
VDD Monitor Supply Current
20
50
Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.
Bit 2:
ESWRST: Enable Software Reset
0: Software reset is not selected as a reset source.
1: Software reset is selected as a reset source.
Bit 1:
EPFRST: Enable Power Fail Reset
0: The power fail detection circuitry (VDD Monitor) is not selected as a reset source.
1: The power fail detection circuitry (VDD Monitor) is selected as a reset source.
Bit 0:
UNUSED. Read = 0b, Write = don’t care.
R/W
Reset Value
ESWRST EPFRST
00000100
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x72
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