Internal Register Definition 1. I2CCLOCK: I2C Clock Frequency Config" />
參數(shù)資料
型號: CP2120EK
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: KIT EVAL FOR CP2120
產(chǎn)品培訓(xùn)模塊: CP21xx USB Bridge
標準包裝: 1
主要目的: 接口,SPI 至 I²C
嵌入式:
已用 IC / 零件: CP2120
次要屬性: LED 狀態(tài)指示器
已供物品: 板,文檔,電源適配器
其它名稱: 336-1325
CP2120
14
Rev. 0.4
Internal Register Definition 1. I2CCLOCK: I2C Clock Frequency Configuration
The transaction time-out counter, which terminates an I2C transaction after a set period of time has passed, can be
configured through the I2CTO Internal Register. If the time-out counter is not enabled, the CP2120 will make only
one attempt at executing an I2C transaction and abort if that transaction attempt fails.
Equation 2. CTO Time-Out Frequency
Internal Register Definition 2. I2CTO: I2C Time Out
The SPI Master can assign an I2C address to the CP2120 by writing to the I2CADR Internal Register. Setting this
address is not necessary for device operation. If set, the CP2120 will ACK this address when another I2C Master
on the bus attempts to communicate with it. The CP2120 will NACK all attempts at data transfer when responding
as an I2C slave.
Internal Register Definition 3. I2CADR: I2C Address
Internal Register Address: 0x02
Reset Value:
0xA0
Bit 7-0:
I2CCK7-0: I2C Clock Frequency Configuration value (minimum register value = 5,
maximum register value = 255)
R/W
I2CCK7
I2CCK6
I2CCK5
I2CCK4
I2CCK3
I2CCK2
I2CCK1
I2CCK0
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
Time-out Frequency
TO
128
---------- Hz
=
Internal Register Address:
0x03
Reset Value:
0x00
Bit 7-1:
TO6-0: Time Out Value
Bit 0:
TEN:Time Out Enable Bit.
0: Disable Timer.
1: Enable Timer.
R/W
TO6
TO5
TO4
TO3
TO2
TO1
TO0
TEN
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
Internal Register Address:
0x05
Reset Value:
0x00
Bit 7-Bit 0:
I2CAD7-0: I2C Address
Sets I2C bus address.
R/W
I2CAD7
I2CAD6
I2CAD5
I2CAD4
I2CAD3
I2CAD2
I2CAD1
I2CAD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
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