參數(shù)資料
型號(hào): CP2120EK
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 24/24頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL FOR CP2120
產(chǎn)品培訓(xùn)模塊: CP21xx USB Bridge
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,SPI 至 I²C
嵌入式:
已用 IC / 零件: CP2120
次要屬性: LED 狀態(tài)指示器
已供物品: 板,文檔,電源適配器
其它名稱: 336-1325
CP2120
Rev. 0.4
9
5. SPI Slave Bus
The CP2120 provides a four-wire slave SPI interface. The CP2120's SPI Bus activates whenever the SPI Master
pulls the NSS pin low. The master can then clock data into the CP2120 through the Master-Out-Slave-In (MOSI)
pin and receive data from the CP2120 through the Master-In-Slave-Out (MISO) pin. The SPI Master provides the
SPI with a clock source. Figure 2 shows typical connections for an SPI bus.
Figure 2. SPI Bus Typical Connections
SCLK should be held high when idle. Figure 3 shows a CP2120 data transfer on the SPI Bus. If the CP2120 is the
only slave device on the SPI bus, the NSS pin can be tied low.
Figure 3. Slave Mode Data/Clock Timing
MISO
MOSI
SPICLK
CS
SCLK
CS
CP2120
SPI Master
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCK
MOSI
MISO
NSS
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