參數(shù)資料
型號(hào): CP2104-F03-GM
廠商: SILICON LABORATORIES
元件分類: 總線控制器
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, QCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220WGGD, QFN-24
文件頁(yè)數(shù): 20/22頁(yè)
文件大?。?/td> 219K
代理商: CP2104-F03-GM
CP2104
Rev. 1.0
7
3. Pinout and Package Definitions
Table 7. CP2104 Pin Definitions
Name
Pin #
Type
Description
VDD
6
Power In
Power Out
Power Supply Voltage Input.
Voltage Regulator Output. See Section 9.
VIO
5
Power In
I/O Supply Voltage Input.
GND
2
Ground. Must be tied to ground.
RST
9D I/O
Device Reset. Open-drain output of internal POR or VDD monitor. An
external source can initiate a system reset by driving this pin low for
the time specified in Table 4.
REGIN
7
Power In
5 V Regulator Input. This pin is the input to the on-chip voltage regu-
lator.
VBUS
8
D In
VBUS Sense Input. This pin should be connected to the VBUS signal
of a USB network.
VPP
16*
Special
Connect a 4.7 F capacitor between this pin and ground to support
ROM programming via USB interface.
D+
3
D I/O
USB D+
D–
4
D I/O
USB D–
TXD
21
D Out
Asynchronous data output (UART Transmit)
RXD
20
D In
Asynchronous data input (UART Receive)
CTS
18*
D In
Clear to Send control input (active low)
RTS
19*
D Out
Ready to Send control output (active low)
DSR
22*
D In
Data Set Ready control input (active low)
DTR
23*
D Out
Data Terminal Ready control output (active low)
DCD
24*
D In
Data Carrier Detect control input (active low)
RI
1*
D In
Ring Indicator control input (active low)
SUSPEND
17*
D Out
This pin is logic high when the CP2104 is in the USB Suspend state.
SUSPEND
15*
D Out
This pin is logic low when the CP2104 is in the USB Suspend state.
GPIO.3
11*
D I/O
User-configurable input or output.
GPIO.2
12*
D I/O
User-configurable input or output.
GPIO.1
13*
D I/O
User-configurable input or output.
GPIO.0
14*
D I/O
User-configurable input or output.
NC
10*
This pin should be left unconnected or tied to VIO.
*Note: Pins can be left unconnected when not used.
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