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參數(shù)資料
| 型號： | COPCH912 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 275K |
| 代理商： | COPCH912 |
Instruction Set
(Continued)
TABLE 7. Instruction Set
(Continued)
Instr
Function
Register Operation
LD
LD
LD
CLRA
INC
DEC
LAID
DCOR
RRC
SWAP
SC
RC
IFC
IFNC
JMPL
JMP
A, [B
±
]
A, [X
±
]
[B
±
], Imm
Load A with Memory [B]
Load A with Memory [X]
Load Memory Immediate
Clear A
Increment A
Decrement A
Load A Indirect from ROM
Decimal Correct A
Rotate Right Through Carry
Swap Nibbles of A
Set C
Reset C
If C
If Not C
Jump Absolute Long
Jump Absolute
A
←
[B] (B
←
B
±
1)
A
←
[X] (X
←
X
±
1)
[B]
←
Imm (B
←
B
±
1)
A
←
0
A
←
A + 1
A
←
A 1
A
←
ROM(PU, A)
A
←
BCD Correction (follows ADC, SUBC)
C
→
A7
→
…
→
A0
→
C
A7…A4
A3…A0
C
←
1
C
←
0
If C is True, do Next Instruction
If C is not True, do Next Instruction
PC
←
ii (ii = 15 Bits, 0k to 32k)
PC11…PC0
←
i (i = 12 Bits)
PC15…PC12 Remain Unchanged
PC
←
PC + r (r is 31 to +32, not 1)
[SP]
←
PL, [SP1]
←
PU, SP2, PC
←
ii
[SP]
←
PL, [SP1]
←
PU, SP2, PC11..PC0
←
ii
PL
←
ROM(PU, A)
SP+2, PL
←
[SP], PU
←
[SP1]
SP+2, PL
←
[SP], PU
←
[SP1],
Skip next Instr.
SP+2, PL
←
[SP], PU
←
[SP1], GIE
←
1
[SP]
←
PL, [SP1]
←
PU, SP2, PC
←
0FF
PC
←
PC+1
A
A
A
A
A
JP
JSRL
JSR
JID
RET
RETSK
Jump Relative Short
Jump Subroutine Long
Jump Subroutine
Jump Indirect
Return from Subroutine
Return and Skip
Addr.
Addr.
Disp.
Addr.
Addr.
RETI
INTR
NOP
Return from Interrupt
Generate an Interrupt
No Operation
Most instructions are single byte (with immediate ad-
dressing mode instructions requiring two bytes).
Most single byte instructions take one cycle time to ex-
ecute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the
skipped instruction opcode.
The following tables show the number of bytes and cycles for
each instruction in the format byte/cycle.
Arithmetic and Logic
Instructions (Bytes/Cycles)
Instr
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
Immediate
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
2/2
2/2
2/2
2/2
2/2
2/2
2/2
Instr
[B]
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
Immediate
2/2
2/2
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
1/3
3/4
3/4
3/4
Instructions Using A and C (Bytes/Cycles)
Instr
Bytes/Cycles
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
CLRA
INCA
DECA
LAID
DCOR
RRCA
SWAPA
SC
RC
C
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PDF描述 |
|---|---|
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相關代理商/技術參數(shù) |
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| COPCH912C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Microcontroller |
| COPCH920C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 1k or 2k |
| COPCH922C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 1k or 2k |
| COPCH940C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 1k or 2k |
| COPCH942C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 1k or 2k |
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