參數(shù)資料
型號(hào)： COPC912
文件頁(yè)數(shù)： 9/20頁(yè)
文件大小： 275K
代理商： COPC912
Functional Description
(Continued)
MICROWIRE/PLUS SLAVE MODE
In MICROWIRE/PLUS Slave mode operation, the SK shift
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G port. The SK pin must be selected as an input and
the SO pin as an output by resetting and setting their respec-
tive bits in the G port configuration register.
The user must set the BUSY flag immediately upon entering
the slave mode. This will ensure that all data bits sent by the
master will be shifted in properly.After eight clock pulses, the
BUSY flag will be cleared and the sequence may be re-
peated.
Note:
In the Slave mode the SIO register does not stop shifting even after the
busy flag goes low. Since SK is an external output, the SIO register
stops shifting only when SK is turned off by the master.
Note:
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK clock for
the SIO register to be narrow. When the BUSY flag is set, the MI-
CROWIRE logic becomes active with the internal SIO shift clock en-
abled. If SK is high in slave mode, this will cause the internal shift clock
to go from low in standby mode to high in active mode. This generates
a rising edge, and causes one bit to be shifted into the SIO register
from the SI input. For safety, the BUSY flag should only be set when
the input SK clock is low.
Note:
The SIO register must be loaded only when the SK shift clock is low.
Loading the SIO register while the SK clock is high will result in unde-
fined data in the SIO register.
Timer/Counter
The device has an on board 16-bit timer/counter (organized
as two 8-bit registers) with an associated 16-bit autoreload/
capture register (also organized as two 8-bit registers). Both
are read/write registers.
The timer has three modes of operation:
PWM (PULSE WIDTH MODULATION) MODE
The timer counts down at the instruction cycle rate (2 μs
max). When the timer count underflows, the value in the au-
toreload register is copied into the timer. Consequently, the
timer is programmable to divide by any value from 1 to
65536. Bit 5 of the timer CNTRL register selects the timer
underflow to toggle the G3 output. This allows the user to
generate a square wave output or a pulse-width-modulated
output. The timer underflow can also be enabled to interrupt
the processor. The timer PWM mode is shown in Figure 7
EXTERNAL EVENT COUNTER MODE
In this mode, the timer becomes a 16-bit external event
counter, clocked from an input signal applied to the G3 input.
The maximum frequency for this G3 input clock is 250 kHz
(half of the 0.5 MHz instruction cycle clock). When the exter-
nal event counter underflows, the value in the autoreload
register is copied into the timer. This timer underflow may
also be used to generate an interrupt. Bit 5 of the CNTRL
register is used to select whether the external event counter
clocks on positive or negative edges from the G3 input. Con-
sequently, half cycles of an external input signal could be
counted. The External Event counter mode is shown in Fig-
ure 8
INPUT CAPTURE MODE
In this mode, the timer counts down at the instruction clock
rate. When an external edge occurs on pin G3, the value in
the timer is copied into the capture register. Consequently,
the time of an external edge on the G3 pin is “captured”. Bit
5 of the CNTRL register is used to select the polarity of the
external edge. This external edge capture can also be pro-
grammed to generate an interrupt. The duration of an input
signal can be computed by capturing the time of the leading
edge, saving this captured value, changing the capture
edge, capturing the time of the trailing edge, and then sub-
tracting this trailing edge time from the earlier leading edge
time. The Input Capture mode is shown in Figure 9
DS012060-8
FIGURE 6. MICROWIRE/PLUS Block Diagram
DS012060-10
FIGURE 7. Timer in PWM Mode
DS012060-11
FIGURE 8. Timer in External Event Mode
C
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