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| 型號(hào)： | COP8SDR9KMTA8 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 46/80頁 |
| 文件大?。?/td> | 972K |
| 代理商： | COP8SDR9KMTA8 |
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14.0 USART
(Continued)
Read/Write, cleared on reset.
CHL1 = 0, CHL0 = 0
CHL1 = 0, CHL0 = 1
CHL1 = 1, CHL0 = 0
CHL1 = 1, CHL0 = 1
The frame contains eight data bits.
The frame contains seven data bits.
The frame contains nine data bits.
Loopback Mode selected. Trans-
mitter output internally looped back
to receiver input. Nine bit framing
format is used.
ERR:
This bit is a global USART error flag which gets set if
any or a combination of the errors (DOE, FE, PE, BD) occur.
Read only; it cannot be written by software, cleared on reset.
RBFL:
This bit is set when the USART has received a
complete character and has copied it into the RBUF register.
It is automatically reset when software reads the character
from RBUF. Read only; it cannot be written by software,
cleared on reset.
TBMT:
This bit is set when the USART transfers a byte of
data from the TBUF register into the TSFT register for trans-
mission. It is automatically reset when software writes into
the TBUF register. Read only, bit is set to “one” on reset; it
cannot be written by software.
ENUR—USART RECEIVE CONTROLAND STATUS REG-
ISTER
(Address at 0BB)
DOE
FE
PE
BD
RBIT9
ATTN
XMTG
RCVG
Bit 7
Bit 0
DOE:
Flags a Data Overrun Error. Read only, cleared on
read, cleared on reset.
DOE = 0
Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register
was read.
DOE = 1
Indicates the occurrence of a Data Overrun
Error.
FE:
Flags a Framing Error. Read only, cleared on read,
cleared on reset.
FE = 0
Indicates no Framing Error has been detected
since the last time the ENUR register was read.
FE = 1
Indicates the occurrence of a Framing Error.
PE:
Flags a Parity Error. Read only, cleared on read, cleared
on reset.
PE = 0
Indicates no Parity Error has been detected since
the last time the ENUR register was read.
PE = 1
Indicates the occurrence of a Parity Error.
BD:
Flags a line break.
BD = 0 Indicates no Line Break has been detected since
the last time the ENUR register was read.
BD = 1 Indicates the occurrence of a Line Break.
RBIT9:
Contains the ninth data bit received when the
USART is operating with nine data bits per frame. Read only,
cleared on reset.
ATTN:
This bit is cleared automatically on receiving a character with
data bit nine set. Read/Write, cleared on reset.
XMTG:
This bit is set to indicate that the USART is transmit-
ting. It gets reset at the end of the last frame (end of last Stop
bit). Read only, cleared on reset.
RCVG:
This bit is set high whenever a framing error or a
Break Detect occurs and goes low when RDX goes high.
Read only, cleared on reset.
ENUI—USART INTERRUPT AND CLOCK SOURCE REG-
ISTER
(Address at 0BC)
STP2
BRK
ETDX
SSEL
XRCLK XTCLK
ERI
ETI
Bit 7
Bit 0
STP2:
This bit programs the number of Stop bits to be
transmitted. Read/Write, cleared on reset.
STP2 = 0
One Stop bit transmitted.
STP2 = 1
Two Stop bits transmitted.
BRK:
Holds TDX (USART Transmit Pin) low to generate a
Line Break. Timing of the Line Break is under software
control.
ETDX:
TDX (USART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
SSEL:
USART mode select. Read only, cleared on reset.
SSEL = 0
Asynchronous Mode.
SSEL = 1
Synchronous Mode.
XRCLK:
This bit selects the clock source for the receiver
section. Read/Write, cleared on reset.
XRCLK = 0
The clock source is selected through the
PSR and BAUD registers.
XRCLK = 1
Signal on CKX (L1) pin is used as the clock.
XTCLK:
This bit selects the clock source for the transmitter
section. Read/Write, cleared on reset.
XTCLK = 0
The clock source is selected through the PSR
and BAUD registers.
XTCLK = 1
Signal on CKX (L1) pin is used as the clock.
ERI:
This bit enables/disables interrupt from the receiver
section. Read/Write, cleared on reset.
ERI = 0
Interrupt from the receiver is disabled.
ERI = 1
Interrupt from the receiver is enabled.
ETI:
This bit enables/disables interrupt from the transmitter
section. Read/Write, cleared on reset.
ETI = 0
Interrupt from the transmitter is disabled.
ETI = 1
Interrupt from the transmitter is enabled.
14.3 ASSOCIATED I/O PINS
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function Port L pin L3, requiring no setup.
Port L pin L2 must be configured as an output in the Port L
Configuration Register in order to be used as the TDX pin.
The baud rate clock for the USART can be generated on-
chip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock I/O pin. The CKX pin can be
either an input or an output, as determined by Port L Con-
figuration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
and/or receiver. As an output, it presents the internal Baud
Rate Generator output.
Note:
The CKX pin is unavailable if Port L1 is used for the
Low Speed Oscillator.
14.4 USART OPERATION
The USART has two modes of operation: asynchronous
mode and synchronous mode.
C
www.national.com
46
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