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| 型號： | COP8SDR9KMTA8 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 972K |
| 代理商： | COP8SDR9KMTA8 |
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13.0 Power Saving Features
(Continued)
13.1 POWER SAVE MODE CONTROL REGISTER
The ITMR control register allows for navigation between the
three different modes of operation. It is also used for the Idle
Timer. The register bit assignments are shown below. This
register is cleared to 40 (hex) by Reset as shown below.
LSON
HSON
DCEN
CCK
SEL
RSVD
ITSEL2
ITSEL1
ITSEL0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSON:
This bit is used to turn-on the low-speed oscilla-
tor. When LSON = 0, the low speed oscillator is
off. When LSON = 1, the low speed oscillator is
on. There is a startup time associated with this
oscillator. See the Oscillator Circuits section.
This bit is used to turn-on the high speed oscil-
lator. When HSON = 0, the high speed oscillator
is off. When HSON = 1, the high speed oscillator
is on. There is a startup time associated with this
oscillator. See the startup time table in the Os-
cillator Circuits section.
This bit selects the clock source for the Idle
Timer. If this bit = 0, then the high speed clock is
the clock source for the Idle Timer. If this bit = 1,
then the low speed clock is the clock source for
the Idle Timer. The low speed oscillator must be
started and stabilized before setting this bit to a
1.
CCKSEL:
This bit selects whether the high speed clock or
low speed clock is gated to the microcontroller
core. When this bit = 0, the Core clock will be the
high speed clock. When this bit = 1, then the
Core clock will be the low speed clock. Before
switching this bit to either state, the appropriate
clock should be turned on and stabilized.
HSON:
DCEN:
DCEN CCKSEL
0
0
High Speed Mode. Core and Idle Timer
Clock = High Speed
Dual Clock Mode. Core clock = High
Speed; Idle Timer = Low Speed
Low Speed Mode. Core and Idle Timer
Clock = Low Speed
Invalid. If this is detected, the Low
Speed Mode will be forced.
1
0
1
1
0
1
RSVD:
Bits 2–0:
These are bits used to control the Idle Timer. See
12.1 TIMER T0 (IDLE TIMER)
for the description
of these bits.
Table 16
lists the valid contents of the four most significant
bits of the ITMR Register. Any other value is illegal. States
are presented in the only valid sequence. Any attempt to
make a transition to any state other than an adjacent valid
state will be ignored by the logic and the ITMR Register will
not be changed.
This bit is reserved and must be 0.
TABLE 16. Valid Contents of Dual Clock Control Bits
LSON
0
1
HSON
1
1
DCEN CCKSEL
0
0
Mode
0
0
High Speed
High Speed/Dual
Clock Transition
Dual Clock
Dual Clock/Low
Speed Transition
Low Speed
1
1
1
1
1
1
0
1
1
0
1
1
10138922
FIGURE 19. Diagram of Power Save Modes
C
www.national.com
38
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