7.0 Timers (Continued) the PMW outputs are useful in controlling motors, triacs, the intensity of displ" />
參數(shù)資料
型號(hào)： COP8SAC7SLB9
廠商： National Semiconductor
文件頁(yè)數(shù)： 15/62頁(yè)
文件大小： 0K
描述： IC MCU OTP 8BIT 4K 28LAMINATECSP
標(biāo)準(zhǔn)包裝： 1
系列： COP8™ 8SA
核心處理器： COP8
芯體尺寸： 8-位
速度： 10MHz
連通性： Microwire/Plus（SPI）
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 24
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-VFQFN，CSP
包裝： 剪切帶 (CT)
其它名稱： *COP8SAC7SLB9
COP8SAC7SLB9CT
7.0 Timers (Continued)
the PMW outputs are useful in controlling motors, triacs, the
intensity of displays, and in providing inputs for data acqui-
sition and sine wave generators.
In this mode, the timer T1 counts down at a fixed rate of t
C.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, R1A and R1B. The very
first underflow of the timer causes the timer to reload from
the register R1A. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register R1B.
The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the
timer for PWM mode operation.
Figure 15 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the T1A output
pin. The underflows can also be programmed to generate
interrupts.
Underflows from the timer are alternately latched into two
pending flags, T1PNDA and T1PNDB. The user must reset
these pending flags under software control. Two control
enable flags, T1ENA and T1ENB, allow the interrupts from
the timer underflow to be enabled or disabled. Setting the
timer enable flag T1ENA will cause an interrupt when a timer
underflow causes the R1A register to be reloaded into the
timer. Setting the timer enable flag T1ENB will cause an
interrupt when a timer underflow causes the R1B register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.
Either or both of the timer underflow interrupts may be
enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to inter-
rupt on both edges of the PWM output.
7.2.2 Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, T1, is clocked by the input signal from the T1A pin. The
T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer
to be clocked either on a positive or negative edge from the
T1A pin. Underflows from the timer are latched into the
T1PNDA pending flag. Setting the T1ENA control flag will
cause an interrupt when the timer underflows.
In this mode the input pin T1B can be used as an indepen-
dent positive edge sensitive interrupt input if the T1ENB
control flag is set. The occurrence of a positive edge on the
T1B input pin is latched into the T1PNDB flag.
Figure 16 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the T1A pin is
being used as the counter input clock.
DS012838-22
FIGURE 15. Timer in PWM Mode
DS012838-23
FIGURE 16. Timer in External Event Counter Mode
COP8SA
Family
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