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| 型號(hào)： | COP8SAC7SLB9 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, QCC28 |
| 封裝： | CSP-28 |
| 文件頁(yè)數(shù)： | 8/60頁(yè) |
| 文件大?。?/td> | 787K |
| 代理商： | COP8SAC7SLB9 |
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AC Electrical Characteristics
0C
≤
T
A
≤
+70C unless otherwise specified.
Parameter
Instruction Cycle Time (t
C
)
Crystal/Resonator, External
Conditions
Min
Typ
Max
Units
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
1.0
2.0
DC
DC
μs
μs
μs
μs
%
%
%
ns
ns
Internal R/C Oscillator
2.0
TBD
R/C Oscillator Frequency Variation
(Note 8)
External CKI Clock Duty Cycle (Note 8)
Rise Time (Note 8)
Fall Time (Note 8)
Inputs
t
SETUP
±
35
TBD
55
12
8
45
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
R
L
= 2.2k, C
L
= 100 pF
200
500
60
150
ns
ns
ns
ns
t
HOLD
Output Propagation Delay (Note 7)
t
PD1
, t
PD0
SO, SK
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
<
4.5V
0.7
1.75
1.0
2.5
μs
μs
μs
μs
ns
ns
ns
All Others
MICROWIRE Setup Time (t
UWS
) (Note 7)
MICROWIRE Hold Time (t
UWH
) (Note 7)
MICROWIRE Output Propagation Delay (t
UPD
)
MICROWIRE Maximum Shift Clock
Master Mode
Slave Mode
Input Pulse Width (Note 7)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
20
56
220
500
1
kHz
MHz
1
1
1
1
1
t
C
t
C
t
C
t
C
μs
Note 2:
t
C
= Instruction cycle time (Clock input frequency divided by 10).
Note 3:
Maximum rate of voltage change must be
<
0.5 V/ms.
Note 4:
Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180 out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 5:
The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of I
DD
HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-
grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
CC
; WATCHDOG and clock monitor disabled.
Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 6:
Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
V
and the pins will have sink current to V
when
biased at voltages
V
(the pins do not have source current when biased at a voltage below V
). The effective resistance to V
is 750
(typical). These two
pins will not latch up. The voltage at the pins must be limited to
14V.
WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
cludes ESD transients.
Note 7:
The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8:
Parameter characterized but not tested.
Note 9:
Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
www.national.com
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