參數(shù)資料
型號(hào): COP8SAC7SLB9
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: 8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory, Power On Reset, and Very Small Packaging
中文描述: 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, QCC28
封裝: CSP-28
文件頁(yè)數(shù): 45/60頁(yè)
文件大小: 787K
代理商: COP8SAC7SLB9
13.0 Instruction Set
(Continued)
JSRL
JSR
JID
RET
RETSK
Addr.
Addr.
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
[SP]
PL, [SP1]
PU,SP2, PC
ii
[SP]
PL, [SP1]
PU,SP2, PC9…0
i
PL
ROM (PU,A)
SP + 2, PL
[SP], PU
[SP1]
SP + 2, PL
[SP],PU
[SP1],
skip next instruction
SP + 2, PL
[SP],PU
[SP1],GIE
1
[SP]
PL, [SP1]
PU, SP2, PC
0FF
PC
PC + 1
RETI
INTR
NOP
RETurn from Interrupt
Generate an Interrupt
No OPeration
13.7 INSTRUCTION EXECUTION TIME
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
1/3
3/4
3/4
3/4
1/1
1/1
1/1
RPND
1/1
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
Transfer of Control Instructions
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
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