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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | COP8CDR9IMT8 |
| 寤犲晢锛� | National Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 102/111闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU CMOS 8BIT 48-TSSOP |
| 妯欐簴鍖呰锛� | 38 |
| 绯诲垪锛� | COP8™ 8C |
| 鏍稿績铏曠悊鍣細 | COP8 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | Microwire/Plus锛圫PI锛�锛孶ART/USART |
| 澶栧湇瑷倷锛� | POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 39 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�32K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 16x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 48-TFSOP锛�0.240"锛�6.10mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | *COP8CDR9IMT8 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�鐣跺墠绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�
SNOS535I 鈥� OCTOBER 2000 鈥� REVISED MARCH 2013
Address
Contents(1)
S/ADD REG
xxFE
B Register
xxFF
S Register
0100 to 017F
On-Chip 128 RAM Bytes
0200 to 027F
On-Chip 128 RAM Bytes
0300 to 037F
On-Chip 128 RAM Bytes
0400 to 0047F
On-Chip 128 RAM Bytes
0500 to 057F
On-Chip 128 RAM Bytes
0600 to 067F
On-Chip 128 RAM Bytes
0700 to 077F
On-Chip 128 RAM Bytes
5.19 Instruction Set
5.19.1 INTRODUCTION
This section defines the instruction set of the COP8 Family members. It contains information about the
instruction set features, addressing modes and types.
5.19.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following features:
Mostly single-byte opcode instructions minimize program size.
One instruction cycle for the majority of single-byte instructions to minimize program execution time.
Many single-byte, multiple function instructions such as DRSZ.
Three memory mapped pointers: two for register indirect addressing, and one for the software stack.
Sixteen memory mapped registers that allow an optimized implementation of certain instructions.
Ability to set, reset, and test any individual bit in data memory address space, including the memory-
mapped I/O ports and registers.
Register-Indirect LOAD and EXCHANGE instructions with optional automatic post-incrementing or
decrementing of the register pointer. This allows for greater efficiency (both in cycle time and program
code) in loading, walking across and processing fields in data memory.
Unique instructions to optimize program size and throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
5.19.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying memory addresses. Each method is called an
addressing mode. These modes are classified into two categories: operand addressing modes and
transfer-of-control addressing modes. Operand addressing modes are the various methods of specifying
an address for accessing (reading or writing) data. Transfer-of-control addressing modes are used in
conjunction with jump instructions to control the execution sequence of the software program.
5.19.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory location is to be affected by that instruction. Several
different operand addressing modes are available, allowing memory locations to be specified in a variety
of ways. An instruction can specify an address directly by supplying the specific address, or indirectly by
specifying a register pointer. The contents of the register (or in some cases, two registers) point to the
desired memory location. In the immediate mode, the data byte to be used is contained in the instruction
itself.
Each addressing mode has its own advantages and disadvantages with respect to flexibility, execution
speed, and program compactness. Not all modes are available with all instructions. The Load (LD)
instruction offers the largest number of addressing modes.
90
Functional Description
Copyright 2000鈥�2013, Texas Instruments Incorporated
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| COP8CDR9KMT7 | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
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