參數(shù)資料
型號： COP8CCR9KMT8
廠商： National Semiconductor
文件頁數(shù)： 52/111頁
文件大?。?/td> 0K
描述： IC MCU EEPROM 8BIT 32K 56-TSSOP
標(biāo)準(zhǔn)包裝： 34
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 49
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
包裝： 管件
其它名稱： *COP8CCR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
The underflows can be programmed to toggle the TxA output pin. The underflows can also be
programmed to generate interrupts.
Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user
must reset these pending flags under software control. Two control enable flags, TxENA and TxENB,
allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag
TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the
timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB
register to be reloaded into the timer. Resetting the timer enable flags will disable the associated
interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of
interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the
user may choose to interrupt on both edges of the PWM output.
Figure 5-10. Timer in PWM Mode
5.11.2.3 Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent PWM mode described above. The main difference
is that the timer, Tx, is clocked by the input signal from the TxA pin after synchronization to the
appropriate internal clock (tC or MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are latched
into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer
underflows.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the
TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the
TxPNDB flag.
Figure 5-11 shows a block diagram of the timer in External Event Counter mode.
NOTE
The PWM output is not available in this mode since the TxA pin is being used as the counter
input clock.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
45
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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參數(shù)描述
COP8CCR9LVA7 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
COP8CCR9LVA7/63 制造商:Texas Instruments 功能描述:
COP8CCR9LVA7/63SN 功能描述:閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
COP8CCR9LVA7/NOPB 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
COP8CCR9LVA763SN 制造商:National Semiconductor 功能描述:MCU 8-bit COP8 CISC 32KB Flash 5V 68-Pin PLCC
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