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參數(shù)資料
| 型號(hào)： | COP8-PGMA-44QFP |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 35/62頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PROGRAMMING ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 附件類(lèi)型： | 編程適配器 |
| 適用于相關(guān)產(chǎn)品： | Cop 8 |
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12.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
RAM
Address
Contents
Select
ADD REG
64 On-Chip RAM Bytes.
02 to 2F
On-Chip RAM (48 Bytes)
(COP8SAAx)
30 to 7F
Unused RAM (Reads as all ones)
128 On-Chip RAM Bytes
00 to 6F
On-Chip RAM (112 Bytes)
(COP8SABx/SACx)
70 to 7F
Unused RAM (Reads as all ones)
80 to 93
Reserved
94
Port F Data Register
95
Port F Configuration Register
96
Port F Input Pins (Read Only)
97
Reserved
A0 to C6
Reserved
C7
WATCHDOG Service Register (Reg: WDSVR)
C8
MIWU Edge Select Register (Reg: WKEDG)
C9
MIWU Enable Register (Reg: WKEN)
CA
MIWU Pending Register (Reg: WKPND)
CB to CF
Reserved
D0
Port L Data Register
D1
Port L Configuration Register
D2
Port L Input Pins (Read Only)
D3
Reserved
D4
Port G Data Register
D5
Port G Configuration Register
D6
Port G Input Pins (Read Only)
D7
Reserved
D8
Port C Data Register
D9
Port C Configuration Register
DA
Port C Input Pins (Read Only)
DB
Reserved
DC
Port D
DD to DF
Reserved
E0 to E5
Reserved
E6
Timer T1 Autoload Register T1RB Lower Byte
E7
Timer T1 Autoload Register T1RB Upper Byte
E8
ICNTRL Register
E9
MICROWIRE/PLUS Shift Register
EA
Timer T1 Lower Byte
EB
Timer T1 Upper Byte
EC
Timer T1 Autoload Register T1RA Lower Byte
ED
Timer T1 Autoload Register T1RA Upper Byte
EE
CNTRL Control Register
EF
PSW Register
F0 to FB
On-Chip RAM Mapped as Registers
FC
X Register
FD
SP Register
FE
B Register
FF
Reserved (Segment Register)
Reading any undefined memory location in the address range of 0080H–00FFH will return undefined data.
COP8SA
Family
www.national.com
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