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參數(shù)資料
| 型號： | CN8333EXF |
| 英文描述： | PCM Transceiver |
| 中文描述： | 收發(fā)器的PCM |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 434K |
| 代理商： | CN8333EXF |
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2.0 Functional Description
CN8331/CN8332/CN8333
2.3 Receiver
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2-10
Conexant
100604B
2.3.4 The PLL Clock Recovery Circuit
The clock recovery circuit (RX PLL) extracts the embedded clock from the sliced
data and provides this clock and the retimed data to the decoder (data mode).
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference
clock (REFCLK, running at the symbol rate) and a phase-frequency detector to
lock to the correct data rate (reference mode). During reference mode, the data
outputs are squelched (set to 0). The RX PLL is kept in reference mode until a
valid input is detected.
2.3.5 Loss Of Signal (LOS) Detector
The Receive Loss Of Signal (RLOS) is a digital function which monitors the
retimed data from the clock recovery block. The AMI data is checked for a
continuous run of zeroes. When a continuous run of 128 ± 1 consecutive zeroes
occurs, the RLOS signal is asserted. After the RLOS signal is asserted, a 1s count
is made on every block of 128 AMI symbols. The RLOS signal is deasserted
when the 1s count within a block of 128 symbols is at least:
B3ZS: Minimum 1s density = 39 ± 1 count out of 128 (~30.5%)
HDB3: Minimum 1s density = 29 ± 1 count out of 128 (~22.7%)
The RLOS detector will always monitor the cable-side RX inputs. The
detector is not affected by the state of remote or local looping.
2.3.6 Jitter Tolerance
The CN833x receiver is able to tolerate a specified amount of high-frequency
jitter in the received signal while providing error-free operation (generally
defined as a bit error rate of less than 10
-9
). The specifications (illustrated in
Figure 2-7
) for jitter tolerance are discussed in the following documents:
E3 rate
–
ITU-T G.823 and
ETSI TBR24
contain frequency masks for input
jitter tolerance.
NOTE:
To meet jitter transfer requirements for loop-timed operation, an external
jitter attenuator is required. The jitter attenuator lessens jitter from the
receive clock.
DS3 rate
–
ITU-T G.823
and
Bellcore GR499
specify jitter tolerance
frequency masks for Category I and Category II interfaces.
STS-1 rate
–
Bellcore GR253
specifies a jitter tolerance. It is noted that the
STS-1 jitter tolerance differs from DS3 requirements only for Category II
interfaces.
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