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參數(shù)資料
| 型號： | CMX218 |
| 英文描述： | ISDN Data and Telephony-Protocol Engine??? |
| 中文描述： | ISDN數(shù)據(jù)和語音通信協(xié)議引擎？？？ |
| 文件頁數(shù)： | 32/34頁 |
| 文件大小： | 353K |
| 代理商： | CMX218 |
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ISDN Data and Telephony Protocol Engine (no X.25)
CMX218
1999
Consumer Microcircuits Limited
1999
Chiron Technology Limited
32
D/218/1
AC Timing Parameters
(continued)
For the following conditions unless otherwise specified:
Xtal Frequency = 32MHz, AV
DD
= DV
DD0
= DV
DD1
= 3.0V to 5.0V, Tamb = - 40°C to +85°C.
Read/Write operation (1/2)
Parameter
Symbol
Conditions
V
DD
= +5.0V ± 10%
Min.
Max.
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time
t
SAST
(0.5 + a) T - 15
(0.5 + a) T - 31
(0.5 + a) T - 17
(0.5 + a) T - 40
0.5T - 24
0.5T - 34
0.5T - 14
(1 + a) T - 9
(1 + a) T - 15
0.5T - 9
0
ASTB high-level width
t
WSTH
V
DD
= +5.0 V ± 10%
Address hold time to (ASTB
↓
)
t
HSTLA
V
DD
- +5.0 V ± 10%
Address hold time (to RD
↑
)
Delay fromaddress to RD
↓
t
HRA
t
DAR
V
DD
= +5.0V ±10%
Address float time (to RD
↓
)
Delay fromaddress to data input
t
FRA
t
DAID
V
DD
= +5.0V ±10%
(2.5 + a + n) T - 37
(2.5 + a + n) T - 52
(2 + n) T - 40
(2 + n) T - 60
(1.5 + n) T - 50
(1.5 + n) T - 70
Delay fromASTB
↓
to data input
t
DSTID
V
DD
= +5.0V ± 10%
Delay fromRD
↓
to data input
t
DRID
V
DD
= +5.0 V ± 10%
Delay fromASTB
↓
to RD
↓
Data hold time (to RD
↑
)
Delay fromRD
↑
to address active
t
DSTR
t
HRID
t
DRA
V
DD
= +5.0 V ± 10%
After programis read
0.5T - 8
ns
After programis read
V
DD
= +5.0 V ± 10%
After data is read
0.5T - 12
ns
1.5T - 8
ns
After data is read
1.5T - 12
0.5T - 17
(1.5 + n) T - 30
(1.5 + n) T - 40
0.5T - 14
(1 + a) T - 5
(1 + a) T - 15
0.5T - 9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay fromRD
↑
to ASTB
↑
RD low-level width
t
DRST
t
WRL
V
DD
= 5.0 V ± 10%
Address hold time (to WR
↑
)
Delay fromaddress to WR
↓
t
HWA
t
DAW
V
DD
= +5.0V ± 10%
Delay fromASTB
↓
to data output
t
DSTOD
V
DD
= +5.0V ± 10%
0.5T + 19
0.5T + 35
0.5T - 11
Delay fromWR
↓
to data output
Delay fromASTB
↓
to WR
↓
t
DWOD
t
DSTW
Where:
T = t
CYK
(system clock cycle time)
a = 1 (during address wait), otherwise, 0
n = Number of wait states (n = 2)
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