參數(shù)資料
型號(hào): CMPWR160SA/R
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: POWER, SOIC-8
文件頁數(shù): 3/9頁
文件大小: 112K
代理商: CMPWR160SA/R
2001 California Micro Devices Corp. All rights reserved. SmartOR
is a trademark of California Micro Devices Corporation.
9/17/2001
3
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CMPWR160
CALIFORNIA MICRO DEVICES
Interface Signals
V
is the input power source for the Low Drop Out
Regulator, capable of delivering 3.3V at the rated
maximum output current even when the input is as low
as 4.2V.
Internal loading on this pin is typically 35μA when the
regulator is enabled, which reduces to only 7μA when-
ever the regulator is shutdown (
SD
taken Low). In the
event of V
collapsing below V
, the loading at V
CC
will
immediately reduce to less than 0.1μA.
If the V
pin is within a few inches of the main input
filter, a capacitor may not be necessary. Otherwise an
input filter capacitor in the range of 1μF to 10μF will
ensure adequate filtering.
SD
is the regulator shutdown input logic signal which is
Active Low. This is a true CMOS input signal referenced
to V
supply. When the pin is tied High (V
) the
regulator operates fully. When the pin is taken to GND,
the device enters shutdown mode and the regulator is
fully disabled. In this mode all critical
POR
circuitry
remains fully powered consuming less than 7μA (typical).
V
is the regulator output voltage used to power the
load. An output capacitor of 10μF is used to provide the
necessary phase compensation, thereby preventing
oscillation. The capacitor also helps to minimize the
peak output disturbance during line or load transients.
Whenever V
collapses below the output the device
immediately enters reverse protection mode to prevent
any current flow back into the regulator pass transistor.
Under these conditions V
will also be used to provide
the necessary quiescent current for the internal refer-
ence and
POR
circuits. This ensures excellent start-up
characteristics for the regulator.
POR
is the Power-Outage-Reset output pin (Active
Low).
Whenever V
falls below the V
threshold (typically
2.9V), this logic output pin is driven low (GND). Upon
V
rising above V
, this pin remains at logic low
(GND) for an additional 30ms duration after which it is
driven to a logic high level (set by V
OUT
).
The Power-Outage-Reset circuitry is powered by, and
draws a very low current (7μA typical) from the V
OUT
rail.
It remains enabled as long as is V
OUT
present and
produces valid logic output signals at the
POR
pin,
even when V
is not present, as would be the case
when V
is driven by an external source (e.g. battery
power) while V
CC
is removed from the CMPWR160.
GND
is the negative reference for all voltages. This
current that flows in the ground connection is very low
(35μA typical with the regulator enabled and 7μA
typical with the regulator disabled).
V
CC
V
CC
5V
SD
GND
GND
POR
V
OUT
V
OUT
3.3V
uP Reset
CMPWR160
10μF
+
C
IN
1μF
C
OUT
+
+
Typical Application Circuit
Pin Functions
Symbol
V
CC
SD
Description
Positive supply input for regulator. When V
CC
falls below V
OUT
the regulator is disabled.
Shutdown control input signal (Active Low) to disable internal voltage regulator and current supply
to less than 7μA.
POR
V
OUT
GND
Power-On-Reset output signal is held Low until the output has been stable (>2.9V) for at least 30ms.
Regulator voltage output (3.3V) when device is enabled (SD is High).
Negative reference for all voltages
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