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參數(shù)資料
| 型號： | CM8872CFI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 76K |
| 代理商： | CM8872CFI |
200
1
California Micro Devices Corp. All rights reserved.
1
2
/
18
/2001
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
6
CM8870/70C
CALIFORNIA MICRO DEVICES
Input Configuration
The input arrangement of the CM8870/70C provides a
differential input operational amplifier as well as a bias
source (V
REF
) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor to
the op-amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are con-
nected as shown in Figure 1, with the op-amp connected
for unity gain and VREF biasing the input at
V
. Figure
6 shows the differential configuration, which permits the
adjustment of gain with the feedback resistor R5.
Clock Circuit
The internal clock circuit is completed with the addition
of a standard television color burst crystal or ceramic
resonator having a resonant frequency of
3.579545MHz. The CM8870C in a PLCC package has a
buffered oscillator output (OSC3) that can be used to
drive clock inputs of other devices such as a micropro-
cessor or other CM887X
’
s as shown in Figure 7. Mul-
tiple CM8870/70Cs can be connected as shown in figure
8 such that only one crystal or resonator is required.
Pin Function
Name
IN+
IN
–
GS
Function
Non-inverting input
Inverting input
Gain select
Reference output Voltage
(nominally V
DD
/2)
Inhibits detection of tones
Digital buffered oscillator output
Power down
Clock input
Discription
V
REF
INH
OSC3
PD
OSC1
Connection to the front-end differential amplifier
Connection to the front-end differential amplifier
Gives access to output of front-end differential amplifier for connection
of feedback resistor.
May be used to bias the inputs at mid-rail.
Represents keys A, B, C, and D
Logic high powers down the device and inhibits the oscillator.
3.579545MHz crystal connected between these pins
completes internal oscillator
OSC2
Clock output
3.579545MHz crystal connected between these pins
completes internal oscillator
TOE
Q
1
Q
2
Q
3
Q
4
StD
V
SS
Negative power supply
Three-state output enable (Input) Logic high enables the outputs Q1-Q4. Internal pull-up.
Three-state ouputs
When enabled by TOE, provides the code corresponding to the last valid
Normally connected to OV
tone pair received. (See Figure 2).
Delayed Steering output
Presents a logic high when a received tone pair has been registered and the
output latch is updated. Returns to logic low shen the voltage on St/GT
falls below V
TSt
.
ESt
Early steering output
Presents logic high immediately when the digital algorithm detects a
recongnizable tone pair (signal condition). Any momentary loss of signal
condition will cause ESt to return to a logic low.
St/Gt
Steering input/guard
time output (bidirectional)
A voltage greater than V
TSt
detected at St causes the device to register
the dectected tone pair. The GT output acts to reset the external steering
time constrant, and its state is a function of ESt and the voltage on St.
(See Figure 2).
V
DD
IC
Positve power supply
Internal connection
Must be tied to V
SS
(for 8870 configuration only).
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