- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379899 > CLC949ACQ (NATIONAL SEMICONDUCTOR CORP) Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter PDF資料下載
參數(shù)資料
| 型號(hào)： | CLC949ACQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 737K |
| 代理商： | CLC949ACQ |
http://www.national.com
6
Figure 3: Transformer Coupled Input
Since the transformer response does not extend to DC it
is not an effective solution for applications which require
DC coupled inputs.
To drive the input of the CLC949, and retain DC
information, an amplifier configuration is required.
Comlinear suggests the use of the circuit shown in Figure 4.
This circuit is used on the E949PCASM.
Figure 4: Amplifier Coupled Input
In this circuit U7 buffers the analog input with a gain of
+1, and U6 buffers the input with a gain of -1. The
circuit has been designed so that U6 and U7 have the
same loop gain, thereby offering the best possible match
of their AC characteristics. U5 is used to generate the
required offset voltages which are summed into the input
signal via U6 and U7. The CLC409 was selected for U6
and U7 due to its current feedback topology which allows
for very low distortion even at high frequencies, and its
excellent phase linearity. Phase match between U6 and
U7 is critical for good pulse response. To generate the
D.C. offsets, the CLC428 dual Op-amp was selected.
The CLC428 is a voltage-feedback op amp with very
good DC characteristics, and the large bandwidth makes
the output impedance low over a wide range of frequen-
cies, allowing good AC performance.
Regardless of how the input is driven, a small capacitor
(15pF) should be added from the V
INP
and V
INN
terminals to GND. This will help to reduce the current
transients that are generated by the CLC949 inputs
during sampling.
Reference Generation
The CLC949 has internally generated reference
voltages. To use these references, you must externally
connect the reference inputs by shorting V
REFPO
to
V
REFP
and V
REFNO
to V
REFN
. During the conversion
cycle, the impedance on these four pins varies
dynamically. To maintain stable biases on these pins you
must bypass them with 0.1
μ
F to GND. If you want to pro-
vide an external reference, then you have to be careful
to provide low output impedance drivers to the V
REFP
and
V
REFN
pins. Bypass capacitors on all reference pins are
recommended for best performance.
Bias Control
One of the unique features of the CLC949 is that it allows
you to set the internal bias current of the device. When
designing an A/D converter a tradeoff is made between
the
amount
of
power
performance. The CLC949 allows you to make this
tradeoff yourself. The bias current is controlled by the
pins BC0 and BC1. These two pins are digital input pins
from which one of three discrete bias points may be
selected (see truth table on page 4 of this datasheet) or
an external bias may be provided through the analog bias
control pin BIASC. If BC0 and BC1 are left open, they
will drift low and provide the default bias condition which
results in 220mW of dissipation at 20MHz sampling rate.
The actual power dissipated by the device is a function
of both the bias condition and the sample rate. The
relationship between power and speed is shown for the
three discrete bias points in Figure 5.
dissipated
and
the
Figure 5: Power Dissipation vs. Sample Rate
As the bias is turned up, the ability of the CLC949 to
handle high frequency inputs and the power dissipation
of the CLC949 increases. To use the BIASC pin, attach
a resistor from the pin to V
DDA
. The current drawn by this
resistor is mirrored in the device to set the internal bias
currents. Asmaller value resistor will result in higher bias
currents and higher performance.Beyond a certain
point, additional improvement is not seen, although
power continues to increase. For this reason, it is
recommended that bias setting resistors of less than
10K not be used. To generate the graph in Figure 6 a
CLC949 was set to sample a signal 1dB below full scale
U5A
-
CLC428
+
1k
1.25k
U5B
-
CLC428
+
1k
U7
-
CLC409
+
500
500
400
500
R7
400
R30
50
R27
50
U6
+
CLC409
-
R29
R8
50
R26
50
V
REFMO
V
INP
V
INN
CLC949
R10
V
IN
15pF
15pF
+5V
+5V
R2
400
+5V
R3
400
V
INP
50
V
REFMO
V
INN
TM01-1T
V
IN
CLC949
15pF
15pF
Power Dissipation vs. Sample Rate
P
Sample Rate (Hz)
400
300
100k
1M
10M
100
0
200
High Bias
40M
Medium Bias
Low Bias
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC949AJQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC952PCASM | CLC949ACQ |
| CLC952 | CLC949ACQ |
| CLC952ACMSA | CLC949ACQ |
| CLC952AJMSA | CLC949ACQ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC949AJQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| CLC952 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CLC949ACQ |
| CLC952 WAF | 制造商:Texas Instruments 功能描述: |
| CLC952ACMSA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC952AJMSA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。