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參數(shù)資料
| 型號： | CLC949ACQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 737K |
| 代理商： | CLC949ACQ |
http://www.national.com
2
PARAMETERS
Case Temperature
CONDITIONS
TYP
MIN/MAX RATINGS
+25
C
0 to 70
C -40 to 85
C
UNITS
SYMBOL
DYNAMIC CHARACTERISTICS
overvoltage recovery V
IN
= 1.5FS
effective aperture delay
aperture jitter
slew rate
settling time
15
3.0
7.0
400
12
25
6.2
15
25
6.2
15
25
6.2
15
ns
ns
OR
TA
AJ
SR
ST
ps(rms)
V/
μ
S
ns
NOISE and DISTORTION (20MSPS)
Signal-to-Noise Ratio (no harmonics)
4.985MHz;
9.663MHz;
Spurious-Free Dynamic Range
4.985MHz;
9.663MHz;
Intermodulation Distortion
f
1
= 5.58MHz @ FS -7dB; f
= 5.70MHz @ FS -7dB
3dB bandwidth (full power)
FS
FS
68
68
66
66
66
66
66
66
dB
dB
SNR2
SNR3
FS -1dB
FS -1dB
72
72
dBc
dBc
SFDR2
SFDR3
63
58
55
-70
100
dBc
MHz
IMD
BW
NOISE and DISTORTION (5MSPS, low bias)
Signal-to-Noise Ratio (no harmonics)
2.4MHz;
Spurious-Free Dynamic Range
2.4MHz;
FS
70
68
68
67
dB
SNR1
FS -1dB
78
66
66
64
dBc
SFDR1
NOISE and DISTORTION (25.6MSPS, high bias)
Signal-to-Noise Ratio (no harmonics)
9.894MHz;
Spurious-Free Dynamic Range
9.894MHz;
FS
67
63
63
63
dB
SNR4
FS-1dB
67
59
53
48
dBc
SFDR4
DC ACCURACY and PERFORMANCE
differential non-linearity
integral non-linearity
common mode rejection ratio
missing codes
mid-scale offset
temperature coefficient
gain error
power supply rejection
V
dda
V
ddd
dc; FS
dc; FS
dc
0.5
1.2
60
0
5.0
15
1.0
1.0
3.5
1.0
3.5
1.0
3.5
LSB
LSB
dB
codes
mV
μ
V/°C
%FS
DNL
INL
CMRR
MC
VIO
DVIO
GE
0
25
0
25
0
25
5.0
5.0
5.0
dc
dc
55
50
dB
dB
PSRA
PSRD
VOLTAGE REFERENCE CHARACTERISTICS
positive reference voltage (internal)
negative reference voltage (internal)
differential reference voltage (Vrefp - Vrefn)
3.25
1.25
2.0
3.24-3.26
1.24-1.26
1.98-2.02
3.24-3.26
1.24-1.26
1.98-2.02
3.24-3.26
1.24-1.26
1.98-2.02
V
V
V
VREFP
VREFN
VDIFF
ANALOG INPUT PERFORMANCE
common mode range
differential range
analog input bias current
analog input capacitance
2 - 3
± 2
±0.1
5.0
V
V
μ
A
pF
VCM
VDM
IBN
CIN
±1.0
10
±1.0
10
±1.0
10
DIGITAL INPUTS
CMOS input voltage
logic LOW
logic HIGH
logic LOW
logic HIGH
1
1
1
V
V
μ
A
μ
A
VIL
VIH
IIL
IIH
4.0
±1.0
±1.0
4.0
±1.0
±1.0
4.0
±1.0
±1.0
CMOS input current
±0.1
±0.1
DIGITAL OUTPUTS
CMOS output voltage
logic LOW
logic HIGH
0.25
4.8
0.5
4.5
0.5
4.5
0.5
4.5
V
V
VOL
VOH
TIMING
maximum conversion rate
minimum conversion rate
data hold time
pipeline delay
30
10
7.0
6.5
30
10
4.5
6.5
30
10
4.5
6.5
30
10
4.5
6.5
MSPS
KSPS
ns
clocks
CR
CRM
THLD
POWER REQUIREMENTS
supply current (+V
dd
)
power dissipation
power dissipation (low bias)
power dissipation (high bias)
44
220
65
400
60
300
60
300
60
300
mA
mW
mW
mW
IDD
PDM
PDL
PDH
20MSPS
5MSPS
30MSPS
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels
are determined from tested parameters.
CLC949 Electrical Characteristics
(+V
DD
= +5V, Medium Bias (200
μ
A): unless specified)
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