參數(shù)資料
型號: CLC935B8C
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-bit, 15MSPS A/D Converter
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP40
封裝: 1.100 INCH, SIDE BRAZED, CERAMIC, DIP-40
文件頁數(shù): 7/12頁
文件大?。?/td> 271K
代理商: CLC935B8C
7
http://www.national.com
Spurious-Free-Dynamic-Range (SFDR)
is the “clean”
dynamic range of the converter, free from harmonic and
spurious signals. SFDR is ratio of the power of the
fundamental compared to the power of the next largest
component in the frequency spectrum. The SFDR
specification is especially important to frequency domain
applications which perform Fourier transforms to analyze
the converter’s output data. Processed applications
like radar and network analyzers are typical areas
where SFDR offers a direct prediction of converter’s
performance at both the system and component levels.
SFDR is the single best specification for selecting a
converter to be used in a frequency domain application.
In-Band Harmonics (IBH)
is the ratio of the power of
the fundamental compared to the power of the single
largest harmonic. This specification is very similar to
SFDR, but since it only considers a fairly limited number
of harmonics, it is potentially an incomplete gauge of
converter performance. SFDR is more stringent and
should be used whenever possible in lieu of IBH.
Typical Frequency Spectrum and its Components
Fundamental
Reference Level
Spurious Free Dynamic Range
Harmonics
Noise
10dB/div (typically)
DC
Nyquist
Increasing Frequency
CLC935 Applications Information
In high-speed data acquisition systems, overall perfor-
mance is often determined by the A/D converter.
Accordingly, special attention should be given to the data
converter, its operation, and its environment. To assist in
this process, information on these critical items has been
included in this data sheet. Additional information on
using high-performance A/D converters can also be
found in application note AD-01.
Principle of Operation
The CLC935 is a complete two step, sub-ranging A/D
converter, with input buffering, internal track-and-hold,
quantizer, and all necessary voltage references. The
block diagram for the CLC935 data converter is shown
below.
CLC935 Functional Block Diagram
The conversion cycle is initiated on the rising edge of the
CONVERT signal. The analog input is sampled by the
track-and-hold amplifier and is then digitized with an 8-
bit digitizer. The 6 MSBs of this conversion are the
“coarse-quantization”, which drive a 14-bit accurate DAC
to match the input level. The DAC output is then sub-
tracted from the original analog input to generate an error
signal, which is then digitized. The two digitized results
are combined to form the 12-Bit accurate output. Error
correction and ECL output buffering is also provided by
the CLC935 converter.
Analog Input Driving Circuits
The high dynamic range of the CLC935 places high
demands on any analog processing circuitry that pre-
cedes the data converter. This is particularly true in the
area of harmonic distortion where the A/Ds’ performance
often exceeds -80dBc. Fortunately, the each employs an
internal buffer for the analog input, and external buffering
circuits are usually not required. Both the CLC207 and
the CLC409 amplifiers can be configured for better than
-80dBc harmonic distortion (note that the CLC207 does
support 12-bit settling performance necessary for “time
domain” applications). This makes them ideal choices for
any analog signal conditioning or buffering that may be
required.
Analog Input Buffering
Gain Adjust
The CLC935 data converter’s input range can be adjust-
ed ±10% from its nominal ±1V range. The input range is
controlled by adjusting the gain of the internal input
buffer. This gain is controlled by the applied voltage at
the GAIN ADJUST (pin33). The relationship between
applied voltage at pin 33 and the analog input range is:
ADC
DAC
REFERENCES
AMP
AMP
A
IN
CONV
CONV
TRACK &
HOLD
CLOCK &
TIMING
O
U
T
P
U
T
B
U
F
F
E
R
D1
.
D12
+
-
A
IN
50
CLC935
CLC409
Analog
Input
1.0V
pp
250
200
250
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