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參數(shù)資料
| 型號(hào)： | CLC5957MTD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 12-bit, 70MSPS Broadband Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 631K |
| 代理商： | CLC5957MTD |
http://www.national.com
8
Figures 5 and 6 show the clock interface schemes to
several other types of clock sources.
Figure 5: 5V CMOS Level Clock Scheme
Figure 6: TTL or 3V CMOS Level Clock Scheme
Digital Outputs and Level Select
Figure 7 depicts the digital output buffer and bias used in
the CLC5957. Although each of the twelve output bits
uses a controlled current buffer to limit supply transients,
it is recommended that parasitic loading of the outputs is
minimized. Because these output transients are harmoni-
cally related to the analog input signal, excessive loading
will degrade ADC performance at some frequencies.
Figure 7: CLC5957 Digital Outputs
The logic high level is slaved to the internal 2.4 voltage
reference. The OUTLEV control pin selects either a 3.3V
or 2.5V logic high level. An internal pullup resistor selects
the 3.3 volt level as the default when the OUTLEV pin is
left open. Grounding the OUTLEV pin selects the 2.5V
logic high level.
To ease user interface to subsequent digital circuitry, the
CLC5957 has a data valid clock output (DAV). In order to
match delays over IC processing variables, this digital
output also uses the same output buffer as the data bits.
The DAV clock output is simply a delayed version of the
ENCODE input clock. Since the ADC output data change
is slaved to the falling edge of the ENCODE clock, the
rising DAV clock edge occurs near the center of the data
valid window (or eye) regardless of the sampling frequency.
ENC
CLC5957
0.01
μ
F
ENC
ENC
CLC5957
0.01
μ
F
ENC
2.4V
ref
GNDD
Digital
V
CCD
Controlled Current
Output Buffer
Digital
Output
Level
Open = 3.3V
hi
GND = 2.5V
hi
CMOS
+
-
+
-
10k
50
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5957MTD/NOPB | 功能描述:CONV A/D 12BIT 70MSPS 48TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:- |
| CLC5957MTDX | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:12-Bit, 70MSPS Broadband Monolithic A/D Converter |
| CLC5957MTDX/NOPB | 功能描述:IC CONV A/D 12BIT MONO 48-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:- |
| CLC5957PCASM | 功能描述:EVALUATION BOARD FOR CLC5957 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類(lèi)型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| CLC5958 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:14-bit, 52MSPS A/D Converter |
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