參數(shù)資料
型號: CLC5957
廠商: National Semiconductor Corporation
英文描述: 12-bit, 70MSPS Broadband Monolithic A/D Converter
中文描述: 12位,70MSPS寬帶單片A / D轉(zhuǎn)換
文件頁數(shù): 2/12頁
文件大小: 631K
代理商: CLC5957
http://www.national.com
2
CLC5957 Electrical Characteristics
(V
cc
= +5V, 66MSPS; unless specified) (T
min
= -40°C, T
max
= +85°C)
PARAMETERS
CONDITIONS
TEMP
RATINGS
TYP
UNITS
NOTES
2
MIN
MAX
RESOLUTION
DIFF. INPUT VOLTAGE RANGE
MAXIMUM CONVERSION RATE
SNR
SFDR
NO MISSING CODES
Full
Full
Full
+25°C
+25°C
+25°C
12
Bits
V
MSPS
dBFS
dBc
1
2.048
75
66
74
70
63
66
1
1
1
1
f
f
f
in
in
in
= 25MHz, A
= 25MHz, A
= 5MHz, A
in
in
= -1dBFS
= -1dBFS
= -1dBFS
in
Guaranteed
DYNAMIC PERFORMANCE
large-signal bandwidth
overvoltage recovery time
effective aperture delay (Ta)
aperture jitter
A
A
in
in
= -3dBFS
= 1.5FS (0.01%)
+25°C
+25°C
+25°C
+25°C
300
12
-0.41
0.3
MHz
ns
ns
ps(rms)
NOISE AND DISTORTION
signal-to-noise ratio (w/o 50 harmonics)
f
in
= 5.0MHz
f
in
= 25MHz
f
in
= 75MHz
f
in
= 150MHz
f
in
= 250MHz
spurious-free dynamic range
f
in
= 5.0MHz
f
in
= 25MHz
f
in
= 75MHz
f
in
= 150MHz
f
in
= 250MHz
intermodulation distortion
f
in1
= 149.84MHz, f
f
in1
= 249.86MHz, f
dithered performance
spurious-free dynamic range
f
in
= 19MHz
intermodulation distortion
f
in1
= 74MHz, f
A
A
A
A
A
in
in
in
in
in
= -1dBFS
= -1dBFS
= -3dBFS
= -15dBFS
= -15dBFS
Full
Full
Full
Full
Full
67
66
65
66
66
dBFS
dBFS
dBFS
dBFS
dBFS
60
1
A
A
A
A
A
in
in
in
in
in
= -1dBFS
= -1dBFS
= -3dBFS
= -15dBFS
= -15dBFS
Full
Full
Full
Full
Full
74
74
72
69
65
dBc
dBc
dBc
dBc
dBc
60
1
in2
in2
= 149.7MHz A
= 249.69MHz A
in
in
= -10dBFS
= -10dBFS
+25°C
+25°C
68
58
dBFS
dBFS
A
in
= -6dBFS
+25°C
85
dBFS
in2
= 75MHz
A
in
= -12dBFS
+25°C
83
dBFS
DC ACCURACY AND PERFORMANCE
differential non-linearity
integral non-linearity
no missing codes
offset error
gain error
V
ref
f
f
f
in
in
in
= 5MHz, A
= 5MHz, A
= 5MHz, A
in
in
in
= -1dBFS
= -1dBFS
= -1dBFS
Full
Full
Full
Full
Full
Full
±0.65
±1.5
LSB
LSB
Guaranteed
0
1.2
2.37
1
1
-30
30
mV
%FS
V
2.2
2.6
1
ANALOG INPUTS
analog differential input voltage range
analog input resistance (single ended)
analog input resistance (differential)
analog input capacitance (single-ended)
Full
Full
Full
Full
2.048
500
1000
2
V
pp
pF
ENCODE INPUTS (Universal)
VIH
VIL
differential input swing
+25°C
+25°C
+25°C
5
V
V
V
3
3
3
0
0.2
DIGITAL OUTPUTS
output voltage
logic LOW
logic HIGH
logic HIGH
+25°C
+25°C
+25°C
0.01
3.5
2.7
0.4
3.8
3.0
V
V
V
1
1
1
OUTLEV = 1 (open)
OUTLEV = 0 (GND)
3.2
2.4
TIMING (C load < 7pF)
maximum conversion rate
minimum conversion rate
pulse width high
pulse width low
pipeline latency
falling ENCODE to output change (50%) (Tod)
rising ENCODE to DAV change (50%) (Tdv)
Full
+25°C
Full
Full
Full
+25°C
+25°C
70
75
10
7.2
7.2
MSPS
MSPS
ns
ns
clk cycle
ns
ns
1
3.0
10
9.6
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