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參數(shù)資料
| 型號： | CLC5903VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | Dual Digital Tuner / AGC |
| 中文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 698K |
| 代理商： | CLC5903VLA |
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26
C
ure 38. The integrator saturates at these limits to prevent
overshoots as the integrator attempts to enter the valid
range. The
AGAIN
value is inverted (
EXP
) and used to
adjust the gain of the incoming signal to provide a linear out-
put dynamic range. The relationship between the DVGA ana-
log gain (
AGAIN
) and the “FIXED TO FLOAT CONVERTER”
digital gain (
EXP
) is shown in Table 4. The DVGA’s compres-
sion of the incoming signal in the analog domain vs. the sub-
sequent expansion in the digital domain is shown in Figure
32.
The AGC may be forced to free run by setting
AGC_HOLD_IC low. Writing an initial condition to
AGC_IC_A|B and then setting AGC_HOLD_IC high will force
the AGC to a fixed gain. The three MSBs of the value written
to AGC_IC_A|B are inverted and output to drive the DVGA.
Allowing the AGC to free run should be appropriate for most
applications. If the INH_EXP bit is not set, the DVGA gain
word (
EXP
) is routed to the “FLOAT TO FIXED CON-
VERTER” in the DDCs prior to the programmable decimation
filter. The
EXP
signals are delayed to account for the propa-
gation delay of the DVGA interface and the CLC5957 ADC.
0
10
20
30
40
50
60
-120
-100
-80
-60
-40
-20
0
20
0
5
10
15
20
25
30
-120
-100
-80
-60
-40
-20
0
20
ADDRESS
A
P
OUT
(dB)
A
(a)
(b)
Figure 37. Example of programmed RAM contents
AGAIN
a
a. AGAIN sets the DVGA or analog gain value.
b. EXP sets the “FIXED TO FLOAT CONVERTER” or digital gain value.
c. 22-bit input to SHIFT-UP block in Figure 16 horizontally, linearized SHIFT-UP value vertically.
d. The numbers in the center of the table represent the mixer output bits. ‘L’ represents a logic low.
EXP
b
Input
c
21
20
19
18
17
16
15
14
...
8
7
6
5
4
3
2
1
0
000 = -12dB
111 = +0dB
-12dB
14
13
12
11
10
9
8
7
...
1
0
L
L
L
L
L
L
L
001 = -6dB
110 = -6dB
-12dB
14
14
13
12
11
10
9
8
...
2
1
0
L
L
L
L
L
L
010 = +0dB
101 = -12dB
-12dB
14
14
14
13
12
11
10
9
...
3
2
1
0
L
L
L
L
L
011 = +6dB
100 = -18dB
-12dB
14
14
14
14
13
12
11
10
...
4
3
2
1
0
L
L
L
L
100 = +12dB
011 = -24dB
-12dB
14
14
14
14
14
13
12
11
...
5
4
3
2
1
0
L
L
L
101 = +18dB
010 = -30dB
-12dB
14
14
14
14
14
14
13
12
...
6
5
4
3
2
1
0
L
L
110 = +24dB
001 = -36dB
-12dB
14
14
14
14
14
14
14
13
...
7
6
5
4
3
2
1
0
L
111 = +30dB
000 = -42dB
-12dB
14
14
14
14
14
14
14
14
...
8
7
6
5
4
3
2
1
0
Table 4. 15-bit Mixer Output Alignment into the 22-bit SHIFT-UP Based On EXP.
d
0
1x2
7
2x2
7
3x2
7
4x2
7
5x2
7
6x2
7
7x2
7
8x2
7
Integrator Output
0
1
2
3
4
5
6
7
A
The min integrator
output must be
limited to 0 so that
the sign of AGAIN
is positive
For this range to be
the same size as all
others, the max
be limited to 8x2
7
-1=2
10
-1
Figure 38. AGC integrator output limits
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| CLC5903VLA/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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