- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379898 > CLC5903VLA (NATIONAL SEMICONDUCTOR CORP) Dual Digital Tuner / AGC PDF資料下載
參數(shù)資料
| 型號： | CLC5903VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | Dual Digital Tuner / AGC |
| 中文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 698K |
| 代理商： | CLC5903VLA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁
25
www.national.com
C
leading ‘1’ out of the CIC filter. An output of ‘001XX’ corre-
sponds to a leading ‘1’ in bit 2 (LSB is bit 0). The exponent
increases by one each time the leading ‘1’ advances in bit
position. The mantissa bits are the two bits that follow the
leading ‘1’. If we define E as the decimal value of the expo-
nent bits and M as the decimal value of the mantissa bits, the
output of the CIC filter, P
OUT
, corresponding to a given
“FIXED TO FLOAT CONVERTER” output is,
(5)
The max() and min() operators account for row 1 of Table 3
which is a special case because M=P
OUT
. Equation 5 associ-
ates each address of the RAM with a CIC filter output.
As shown in Figure 34, the 32X8 RAM look-up table imple-
ments the functions of log converter, reference subtraction,
error amplifier, and deadband. The user must build each of
these functions by constructing a set of 8-bit, 2’s complement
numbers to be loaded into the RAM. Each of these functions
and how to construct them are discussed in the following
paragraphs.
A log conversion is done in order to keep the loop gain inde-
pendent of operating point. To see why this is beneficial, the
control gain of the DVGA computed without log conversion is,
(6)
where G is the decimal equivalent of GAIN and G
o
accounts
for the DVGA gain in excess of unity. This equation assumes
that the DVGA gain control polarity is positive as is the case
for the CLC5526. The gain around the entire loop must be
negative. Observe in Equation 6 that the control gain is
dependent on operating point G. If we instead compute the
control gain with log conversion,
(7)
which is no longer operating-point dependent. The log func-
tion is constructed by computing the CIC filter output associ-
ated with each address (Equation 5) and converting these to
dB. Full scale (dc signal) is
20
.
The reference subtraction is constructed by subtracting the
desired loop servo point (in dB) from the table values com-
puted in the previous paragraph. For example, if it is desired
that the DVGA servo the ADC input level (sinusoidal signal)
to -6dBFS, the number to subtract from the data is
.
(8)
The table data will then cross through zero at the address
corresponding to this reference level. A deadband wider than
6dB should then be constructed symmetrically about this
point. This prevents the loop from hunting due to the 6dB
gain steps of the DVGA. Any deadband in excess of 6dB
appears as hysteresis in the servo point of the loop as illus-
trated in Figure 33. The deadband is constructed by loading
zeros into those addresses on either side of the one which
corresponds to the reference level.
The last function of the RAM table is that of error amplifica-
tion. All the operations preceding this one gave a table slope
. This must now be adjusted in order to control the
time constant of the loop given by,
(9)
The term G
L
in this equation is the loop gain,
(10)
The design equations are obtained by solving Equation 9 for
G
L
and Equation 10 for
trol register value that determines the number of bits to shift
the output of the RAM down by. This allows some of the loop
gain to be moved out of the RAM so that the full output range
of the table is utilized but not exceeded. The valid range for
AGC_LOOP_GAIN is from 0 to 3 which corresponds to a 1 to
4 bit shift left.
An example set of numbers to implement a loop having a ref-
erence of 6dB below full scale, a deadband of 8dB, and a
loop gain of 0.108 is:
-102 -102 -88 -80 -75 -70 -66
-63 -61 -56 -53 -50
-47 -42 -39 -36 -33 -29 -25
-22 -19 -15 -11 0
0 0 0 0 0 13 17 20
These values are shown plotted in Figure 37 with respect to
the table addresses in (a), and the CIC filter output P
OUT
in
(b). For a 52MHz clock rate and AGC_LOOP_GAIN=2, these
values result in a loop time constant of
. AGC_LOOP_GAIN is a con-
.
The error signal from the loop gain “SHIFT DOWN” circuit is
gated into the loop integrator. The gate is controlled by a tim-
ing and control circuit discussed in the next paragraph. A
MUX within the integrator feedback allows the integrator to
be initialized to the value loaded into AGC_IC_A (channel B
can be set independently). The conditions under which it is
initialized are configured in the registers associated with the
timing and control circuit. The top eight bits of the integrator
output can also be read back over the microprocessor inter-
face from the AGC_RB_A (or AGC_RB_B) register. The top
3 bits below
the sign become
AGAIN
and are output along
with
ASTROBE
signal on the DVGA interface pins. The valid
range of
AGAIN
is from 0 to 7 which corresponds to a valid
range of 0 to 2
10
-1 for the 11-bit, 2’s complement integrator
output from which
AGAIN
is derived. This is illustrated in Fig-
INPUT
OUTPUT
(eeemm)
0-3
000XX
4-7
001XX
8-15
010XX
16-31
011XX
32-63
100XX
64-127
101XX
128-255
110XX
256-511
111XX
Table 3. Fixed to Float Converter Truth Table
P
OUT
4
min E
1
2
max E
1
,
)
,
)
1
M
+
)
E
,
[
]
≥
–
(
1.
=
K
DVGA
′
G
v
i
2
G
G
o
–
(
)
(
)
,
=
v
i
2
( )
2
G
G
o
–
(
)
,
ln
–
=
K
DVGA
G
6.02,
–
20
v
i
2
G
G
o
–
(
)
(
)
log
[
]
,
=
=
511
(
)
54
dB
=
log
20
2
511
2
π
--
44
dB
=
log
S
RAM
1
=
τ
F
CK
----8
G
L
--1
1
2
--
+
.
=
G
L
6.02
S
RAM
2
AGC_LOOP_GAIN
8
–
(
)
.
–
=
S
RAM
1.5
μ
s
AGC Theory of Operation
(Continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC5955 | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTDX | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5956PCASM | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
| CLC5956 | 12-bit, 65 MSPS Broadband Monolithic A/D Converter(12位65 MSPS寬帶單片A/D轉(zhuǎn)換器) |
| CLC5956IMTD | 12-bit, 65 MSPS Broadband Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903VLA/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5955 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| CLC5955MTD/NOPB | 功能描述:ADC 11BIT 55MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| CLC5955MTDX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:11-bit, 55MSPS Broadband Monolithic A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。