
Application Information
Low Noise Design
Ultimate low noise performance from circuit designs using
the CLC5802 requires the proper selection of external resis-
tors. By selecting appropriate low-valued resistors for R
f
and
R
, amplifier circuits using the CLC5802 can achieve output
noise that is approximately the equivalent voltage input
noise of 4nV/
multiplied by the desired gain (A
V
).
Each amplifier in the CLC5802 has an equivalent input noise
resistance which is optimum for matching source imped-
ances of approximately 2k. Using a transformer, any source
can be matched to achieve the lowest noise design.
For even lower noise performance than the CLC5802, con-
sider the CLC425, CLC426 or CLC5801 at 1.05, 1.6 and
2nV/
, respectively.
DC Bias Currents and Offset Voltages
Cancellation of the output offset voltage due to input bias
currents is possible with the CLC5802. This is done by mak-
ing the resistance seen from the inverting and non-inverting
inputs equal. Once done, the residual output offset voltage
will be the input offset voltage (V
) multiplied by the desired
gain (A
). Application Note OA-7 offers several solutions to
further reduce the output offset.
Output and Supply Considerations
With
±
5V supplies, the CLC5802 is capable of a typical out-
put swing of
±
3.6V under a no-load condition.Additional out-
put swing is possible with slightly higher supply voltages. For
loads of less than 50
, the output swing will be limited by the
CLC5802’s output current capability, typically 70mA.
Output settling time when driving capacitive loads can be im-
proved by the use of a series output resistor. See the plot la-
beled “Settling Time vs. Capacitive Load” in the Typical Per-
formance Characteristics section.
Layout
Proper power supply bypassing is critical to insure good high
frequency performance and low noise. De-coupling capaci-
tors of 0.1μF should be placed as close as possible to the
power supply pins. The use of surface mounted capacitors is
recommended due to their low series inductance.
A good high frequency layout will keep power supply and
ground traces away from the inverting input and output pins.
Parasitic capacitance from these nodes to ground causes
frequency response peaking and possible circuit oscillation.
See OA-15 for more information. National suggests the
CLC730038 (through-hole) or the CLC730036 (SOIC) dual
op amp evaluation board as a guide for high frequency lay-
out and as an aid in device evaluation.
Full Duplex Digital or Analog Transmission
Simultaneous transmission and reception of analog or digital
signals over a single coaxial cable or twisted-pair line can re-
duce cabling requirements. The CLC5802’s wide bandwidth
and high common-mode rejection in a differential amplifier
configuration allows full duplex transmission of video, tele-
phone, control and audio signals.
In the circuit shown in Figure 1 one of the CLC5802’s amps
is used as a “driver” and the other as a difference “receiver”
amplifier. The output impedance of the “driver” is essentially
zero. The two R’s are chosen to match the characteristic im-
pedance of the transmission line. The “driver” op amp gain
can be selected for unity or greater.
Receiver amplifier A
(B
) is connected across R and forms
a differential amplifier for the signals transmitted by driver A
1
(B
1
). If the coax cable is lossless and R
f
equals R
g
, receiver
A
2
(B
2
) will then reject the signals from driver A
1
(B
1
) and
pass the signals from driver B
1
(A
1
).
The output of the receiver amplifier will be:
(1)
Care must be given to layout and component placement to
maintain a high frequency common-mode rejection. The plot
of Figure 2show the simultaneous reception of signals trans-
mitted at 1MHz and 10MHz.
Five Decade Integrator
A composite integrator, shown in Figure 3 uses the
CLC5802 dual op amp to increase the circuits usable fre-
quency range of operation. The transfer function of this cir-
cuit is:
(2)
DS101341-28
FIGURE 1.
DS101341-25
FIGURE 2.
DS101341-27
FIGURE 3.
C
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