
2nd and 3rd Harmonic Distortion
To meet low distortion requirements, recognize the effect
of the feedback resistor.
resistor will decrease the loop gain and increase
distortion. Decreasing the load impedance increases 3rd
harmonic distortion more than 2nd.
Increasing the feedback
Differential Gain and Differential Phase
The CLC5665 has low DG and DP errors for video
applications. Add an external pulldown resistor to the
CLC5665’s output to improve DG and DP as seen in
Figure 4. A 604
R
p
will improve DG and DP to 0.01%
and 0.02°.
Figure 4: Improved DG and DP Video Amplifier
Printed Circuit Layout
To get the best amplifier performance careful placement
of the amplifier, components and printed circuit traces
must be observed. Place the 0.1
μ
F ceramic decoupling
capacitors less than 0.1” (3mm) from the power supply
pins.
Place the 6.8
μ
F tantalum capacitors less than
0.75” (20mm) from the power supply pins. Shorten traces
between the inverting pin and components to less
than 0.25” (6mm). Clear ground plane 0.1” (3mm) away
from pads and traces that connect to the inverting, non-
inverting and output pins. Do not place ground or power
plane beneath the op-amp package. National provides
literature and evaluation boards CLC730013 DIP or
CLC730027 SOIC illustrating the recommended op-amp
layout.
Level Shifting
The circuit shown in Figure 5 implements level shifting by
AC coupling the input signal and summing a DC voltage.
The resistor R
in
and the capacitor C set the high-pass
break frequency. The amplifier closed-loop bandwidth is
fixed by the selection of R
f
. The DC and AC gains for
circuit of Figure 5 are different.The AC gain is set by the
ratio of R
f
and R
g
. And the DC gain is set by the parallel
combination of R
g
and R
2
.
Figure 5: Level Shifting Circuit
Multiplexing
Multiple signal switching is easily handled with the dis-
able function of the CLC5665. Board trace capacitance
at the output pin will affect the frequency response and
switching transients. To lessen the effects of output
capacitance place a resistor (R
o
) within the feedback
loop to isolate the outputs as shown in Figure 6.To match
the mux output impedance to a transmission line, add a
resistor (R
s
) in series with the output.
Figure 6: Output Connection for
Multiplexing Circuits
Differential Line Driver With Load
Impedance Conversion
The circuit shown in Figure 7, operates as a differential
line driver. The transformer converts the load impedance
to a value that best matches the CLC5665’s output
capabilities. The single-ended input signal is converted
to a differential signal by the CLC5665. The line’s
characteristic impedance is matched at both the input
and the output.The schematic shows Unshielded Twisted
Pair for the transmission line;other types of lines can also
be driven.
Figure 7: Differential Line Driver with
Load Impedance Conversion
5
http://www.national.com
V
in
-V
cc
V
out
Add R to
improve
DG and DP
R
p
R
f
R
g
R
s
R
in
CLC5665
-
+
Applications Circuits
V
V
R
R
R
V
R
R
out
in
f
g
in
f
ac
DC
=
+
1
2
2
C
V
in
DC
V
in
AC
V
out
R
f
R
g
R
2
R
in
+
-
CLC5665
R
f
R
f
R
s
R
o
R
o
R
in
R
in
R
L
R
g
R
g
V
out
V
in1
V
in2
DIS1
DIS2
CLC5665
CLC5665
-
+
+
-
+
CLC5665
-
R
g2
+
V
o
-
-
CLC5665
+
R
t2
R
f2
R
f1
R
g1
V
in
R
t1
R
m/2
R
m/2
R
L
Z
o
UTP
I
o
R
eq
1:n
V
d/2
-V
d/2