參數(shù)資料
型號(hào): CLC5665IM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運(yùn)動(dòng)控制電子
英文描述: Low Distortion Amplifier with Disable
中文描述: OP-AMP, 10000 uV OFFSET-MAX, 90 MHz BAND WIDTH, PDSO8
封裝: PLASTIC, SOIC-8
文件頁數(shù): 4/8頁
文件大?。?/td> 120K
代理商: CLC5665IM
http://www.national.com
4
The CLC5665 is a general purpose current-feedback
amplifier for use in a variety of small- and large-signal
applications. Use the feedback resistor to fine tune the
gain flatness and -3dB bandwidth for any gain setting.
National provides information for the performance at a
gain of +2 for small and large signal bandwidths. The
plots show feedback resistor values for selected gains.
Gain
Use the following equations to set the CLC5665’s non-
inverting or inverting gain:
Choose the resistor values for non-inverting or inverting
gain by the following steps.
Figure 1: Component Identification
1) Select the recommended feedback resistor R
f
.
2) Choose the value of R
g
to set gain.
3) Select R
s
to set the circuit output impedance.
4) Select R
in
for input impedance and input bias.
High Gains
Current feedback closed-loop bandwidth is independent
of gain-bandwidth-product for small gain changes. For
larger gain changes the optimum feedback register R
f
is
derived by the following:
R
f
= 724
– 60
(A
v
)
As gain is increased, the feedback resistor allows band-
width to be held constant over a wide gain range. For a
more complete explanation refer to application note OA-25:
Stability Analysis of Current-Feedback Amplifiers
.
Resistors have varying parasitics that affect circuit
performance in high-speed design. For best results, use
leaded metal-film resistors or surface mount resistors. A
SPICE model for the CLC5665 is available to simulate
overall circuit performance.
Enable/Disable Function
The CLC5665 amplifier features an enable/disable
function that changes the output and inverting input from
low to high impedance. The pin 8 enable/disable logic
levels are as follows:
V
CC
Enable
Disable
±15V
>12.7V
<10.0V
±5V
>2.7V
<0.8V
The amplifier is enabled with pin 8 left open due to the
2k
pull-up resistor, shown in Figure 2.
Figure 2: Pin 8 Equivalent Disable Circuit
Open-collector or CMOS interfaces are recommended to
drive pin 8. The turn-on and off time depends on the
speed of the digital interface.
The equivalent output impedance when disabled is
shown in Figure 3. With R
g
connected to ground, the sum
of R
f
and R
g
dominates and reduces the disabled output
impedance. To raise the output impedance in the dis-
abled state, connect the CLC5665 as a unity-gain
voltage follower by removing R
g
. Current-feedback
op-amps need the recommended R
f
in a unity-gain
follower circuit. For high density circuit layouts consider
using the dual CLC431 (with disable) or the dual CLC432
(without disable).
Figure 3: Equivalent Disabled Output Impedance
Non InvertingGain
1
R
R
InvertingGain
-R
R
f
g
f
g
=
+
=
R
in
R
g
R
f
CLC5665
-
+
V
in
V
o
R
s
To CLC5665
Bias network
2k
+
V
cc
Pin 8 DISABLE
8k
-
V
cc
Equivin Disable
R
f
V
out
R
g
V
in
300k
8pF
+
-
Z
o
)
Frequency (MHz)
1
10
100
1
10
100
1k
10k
100k
1M
CLC5665 Design Considerations
相關(guān)PDF資料
PDF描述
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