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參數(shù)資料
| 型號： | CLC5633IN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Triple, High Output, Programmable Gain Buffer |
| 中文描述： | TRIPLE BUFFER AMPLIFIER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 271K |
| 代理商： | CLC5633IN |
Application Division
(Continued)
Layout Considerations
A proper printed circuit layout is essential for achieving high
frequency performance. National provides evaluation boards
for the CLC5633 (CLC730075-DIP, CLC730074-SOIC) and
suggests their use as a guide for high frequency layout and
as an aid for device testing and characterization.
General layout and supply bypassing play major roles in high
frequency performance. Follow the steps below as a basis
for high frequency layout:
Include 6.8μF tantalum and 0.1μF ceramic capacitors on
both supplies.
Place the 6.8μF capacitors within 0.75 inches of the
power pins.
Place the 0.1μF capacitors less than 0.1 inches from the
power pins.
Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance.
Use flush-mount printed circuit board pins for prototyping,
never use high profile DIP sockets.
Evaluation Board Information
A data sheet is available for the CLC730075/CLC730074
evaluation boards. The evaluation board data sheets pro-
vide:
Evaluation board schematics
Evaluation board layouts
General information about the boards
The evaluation boards are designed to accommodate dual
supplies. The boards can be modified to provide single
supply operation. For best performance; 1) do not connect
the unused supply, 2) ground the unused supply pin.
Special Evaluation Board
Considerations for the CLC5633
To optimize off-isolation of the CLC5633, cut the R
trace on
both the CLC730074 and the CLC730075 evaluation
boards. This cut minimizes capacitive feedthrough between
the input and the output.
SPICE Models
SPICE models provide a means to evaluate amplifier de-
signs. Free SPICE models are available for National’s mono-
lithic amplifiers that:
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise perfor-
mance
Support room temperature simulations
The
readme
file that accompanies the diskette lists released
models, and provides a list of modeled parameters. The
application note OA-18, Simulation SPICE Models for Na-
tional’s OpAmps, contains schematics and a reproduction of
the readme file.
Application Circuits
Single Supply Cable Driver
Figure 13 below shows the CLC5633 driving 10m of 75
coaxial cable. The CLC5633 is set for a gain of +2V/V to
compensate for the divide-by-two voltage drop at V
O
. The
response after 10m of cable is illustrated in Figure 14
CLC5633
0.1
μ
F
6.8
μ
F
+
+5V
Note:
Channel 2 and 3 not shown.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
in
5k
5k
+5V
0.1
μ
F
0.1
μ
F
75
V
o
0.1
μ
F
75
10m of 75
DS015005-52
FIGURE 13. Single Supply Cable Driver
1
20ns/div
V
in
= 10MHz, 0.5V
pp
DS015005-53
FIGURE 14. Response After 10m of Cable
C
www.national.com
15
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