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參數(shù)資料
| 型號(hào)： | CLC5633IN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Triple, High Output, Programmable Gain Buffer |
| 中文描述： | TRIPLE BUFFER AMPLIFIER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | CLC5633IN |
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Application Division
(Continued)
Driving Cables and Capacitive Loads
When driving cables, double termination is used to prevent
reflections. For capacitive load applications, a small series
resistor at the output of the CLC5633 will improve stability
and settling performance. The Frequency Response vs. CL
plot, shown below in Figure 10 gives the recommended
series resistance value for optimum flatness at various ca-
pacitive loads.
Transmission Line Matching
One method for matching the characteristic impedance (Z
o
)
of a transmission line or cable is to place the appropriate
resistor at the input or output of the amplifier. Figure 11
shows typical inverting and non-inverting circuit configura-
tions for matching transmission lines.
Non-Inverting gain applications:
Connect pin 2 as indicated in the table in the
Closed
Loop Gain Selection
section.
Make R
1
, R
2
, R
6
, and R
7
equal to Z
O
.
Use R
to isolate the amplifier from reactive loading
caused by the transmission line, or by parasitics.
Inverting gain applications:
Connect R
3
directly to ground.
Make the resistors R
4
, R
6
, and R
7
equal to Z
O
.
Make R
5
\
R
g
=Z
O
.
The input and output matching resistors attenuate the signal
by a factor of 2, therefore additional gain is needed. Use C
6
to match the output transmission line over a greater fre-
quency range. C
compensates for the increase of the am-
plifier’s output impedance with frequency.
Power Dissipation
Follow these steps to determine the power consumption of
the CLC5633:
1. Calculate the quiescent (no-load) power: P
amp
=I
CC
(V
CC
-
V
EE
)
2. Calculate the RMS power at the output stage: P
=(V
-
V
)(I
), where V
and I
are the RMS voltage
and current across the external load.
3. Calculate the total RMS power: P
t
=P
amp
+P
O
The maximum power that the DIP and SOIC, packages can
dissipate at a given temperature is illustrated in Figure 12
The power derating curve for any CLC5633 package can be
derived by utilizing the following equation:
where
T
amb
= Ambient temperature (C)
θ
= Thermal resistance, from junction to ambient, for a
given package (C/W)
M
Frequency (Hz)
1M
10M
100M
V
o
= 1V
pp
C
L
= 10pF
R
s
= 49.9
C
L
= 100pF
R
s
= 21
C
L
= 1000pF
R
s
= 6.7
L
1k
R
s
+
-
1k
1k
DS015005-48
FIGURE 10. Frequency Response vs. CL
CLC5633
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
Note:
Channel 2 and 3 not shown.
Z
0
R
4
R
5
+
V
1
R
3
Z
0
R
1
R
2
V
2
+
Z
0
R
6
V
o
C
6
R
7
DS015005-49
FIGURE 11. Transmission Line Matching
DS015005-51
FIGURE 12. Power Derating Curve
C
www.national.com
14
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