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參數(shù)資料
| 型號： | CLC5633 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Triple, High Output, Programmable Gain Buffer |
| 中文描述： | 三，產(chǎn)量高，可編程增益緩沖器 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 271K |
| 代理商： | CLC5633 |
Application Division
(Continued)
The input is AC coupled to prevent the need for level shifting
the input signal at the source. The resistive voltage divider
biases the non-inverting input to V
CC
÷ 2 = 2.5V (For V
CC
=
+5V).
Dual Supply Operation
The CLC5633 operates on dual supplies as well as signal
supplies. The non-inverting and inverting configurations are
shown in Figure 7 Figure 8 and Figure 9
Load Termination
The CLC5633 can source and sink near equal amounts of
current. For optimum performance, the load should be tied to
V
CM
.
CLC5633
0.1
μ
F
6.8
μ
F
+
V
CC
Note:
Channel 2 and 3 not shown.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
Low frequency cutoff
where Rg = 1k
.
V
2.5
1
2 R C
π
o
in
C
=
+
=
,
V
in
R
R
V
CC
C
C
V
o
DS015005-42
FIGURE 4. AC Coupled, A
V
= 1V/V Configuration
CLC5633
0.1
μ
F
6.8
μ
F
+
V
CC
Note:
Channel 2 and 3 not shown.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
o
V
in
R
R
V
CC
C
C
V
Low frequency cutoff
2V
2.5
1
2 R C
R
source
whereR
R
2
R
o
C
in
=
+
=
=
>>
,
C
DS015005-43
FIGURE 5. AC Coupled, A
V
= +1V/V Configuration
CLC5633
0.1
μ
F
6.8
μ
F
+
V
CC
Note:
Channel 2 and 3 not shown.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
o
V
in
R
R
V
CC
C
C
V
Low frequency cutoff
2V
2.5
1
2 R C
R
source
whereR
R
2
R
C
in
=
+
=
=
>>
,
C
DS015005-44
FIGURE 6. AC Coupled, A
V
= +2V/V Configuration
CLC5633
0.1
μ
F
6.8
μ
F
+
V
CC
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
o
V
in
R
t
R
b
provides DC bias fo to
t
Note:
in
= R
t
||1k
.
Channel 2 and 3 not shown.
R
b
6.8
μ
F
0.1
μ
F
+
V
EE
DS015005-45
FIGURE 7. Dual Supply, A
V
= 1V/V Configuration
CLC5633
0.1
μ
F
6.8
μ
F
+
V
CC
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
o
V
in
R
t
Note:
Channel 2 and 3 not shown.
6.8
μ
F
0.1
μ
F
+
V
EE
DS015005-46
FIGURE 8. Dual Supply, A
V
= +1V/V Configuration
CLC5633
0.1
μ
F
6.8
μ
F
+
V
CC
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
o
V
in
R
t
Note:
Channel 2 and 3 not shown.
6.8
μ
F
0.1
μ
F
+
V
EE
DS015005-47
FIGURE 9. Dual Supply, A
V
= + 2V/V Configuration
C
www.national.com
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC5633IM | Triple, High Output, Programmable Gain Buffer |
| CLC5633IMX | Triple, High Output, Programmable Gain Buffer |
| CLC5633IN | Triple, High Output, Programmable Gain Buffer |
| CLC5644 | Low-Power, Low-Cost, Quad Operational Amplifier |
| CLC5644IM | Low-Power, Low-Cost, Quad Operational Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5633IM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Triple, High Output, Programmable Gain Buffer |
| CLC5633IMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Triple, High Output, Programmable Gain Buffer |
| CLC5633IN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CLC5633M/N WAF | 制造商:Texas Instruments 功能描述: |
| CLC5644 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Power, Low-Cost, Quad Operational Amplifier |
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