參數(shù)資料
型號(hào)： CLC5633
廠商： National Semiconductor Corporation
英文描述： Triple, High Output, Programmable Gain Buffer
中文描述： 三，產(chǎn)量高，可編程增益緩沖器
文件頁(yè)數(shù)： 12/17頁(yè)
文件大?。?/td> 271K
代理商： CLC5633
Application Division
(Continued)
The denominator of Equation 1 is approximately equal to 1 at
low frequencies. Near the 3dB corner frequency, the inter-
action between R
and Z(j
ω
) dominates the circuit perfor-
mance. The value of the feedback resistor has a large affect
on the circuits performance. Increasing R
f
has the following
affects:
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
CLC5633 Design Information
Closed Loop Gain Selection
The CLC5633 is a current feedback op amp with R
= R
=
1k
on chip (in the package). Select from three closed loop
gains without using any external gain or feedback resistors.
Implement gains of +2, +1, and 1V/V by connecting pins 5
and 6 (or 9 and 10, or 12 and 13) as described in the chart
below.
Z(j
ω
) is the CLC5633’s open loop transimpedance gain
Z(j
ω
)/R
f
is the loop gain
Gain A
V
Input Connections
Non-Inverting
(pins 5, 10, &
12)
ground
input signal
input signal
Inverting (pins 6,
9, & 13)
1V/V
+1V/V
+2V/V
The gain accuracy of the CLC5633 is excellent and stable
over temperature change. The internal gain setting resistors,
R
and R
are diffused silicon resistors with a process varia-
tion of
±
20% and a temperature coefficient of 2000ppm/C.
Although their absolute values change with processing and
temperature, their ratio (R
/R
) remains constant. If an exter-
nal resistor is used in series with R
g
, gain accuracy over
temperature will suffer.
Single Supply Operation (V
CC
=+5V, V
EE
=GND)
The specifications given in the
+5V Electrical Characteris-
tics
table for single supply operation are measured with a
common mode voltage (V
) of 2.5V. V
is the voltage
around which the inputs are applied and the output voltages
are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5633 is typically +0.8V to
+4.2V. The typical output range with R
L
=100
is +1.0V to
+4.0V.
For single supply DC coupled operation, keep input signal
levels above 0.8V DC, AC coupling and level shifting the
signal are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in the
following 2 sections.
DC Coupled Single Supply Operation
Figure 1 Figure 2 and Figure 3 on the following page, show
the recommended configurations for input signals that re-
main above 0.8V DC. Note: R
provides DC bias for the
non-inverting input. R
, R
and R
are tied to V
for mini-
mum power consumption and maximum output swing. Chan-
nel 2 and 3 not shown.
input signal
NC (open)
ground
AC Coupled Single Supply Operation
Figure 4 Figure 5 and Figure 6 show possible non-inverting
and inverting configurations for input signals that go below
0.8V DC.
CLC5633
V
in
R
t
V
cm
0.1
μ
F
6.8
μ
F
+
V
CC
V
o
R
L
V
cm
Note:
R
provides DC bias for the non-inverting input. R
, R
L
and R
t
are tied to V
cm
for minimum power consumption and maximum output swing.
Channel 2 and 3 not shown.
R
b
V
cm
Select R
t
to yield desired R
in
= R
t
||R
g
, where R
g
= 1k
.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
DS015005-39
FIGURE 1. DC Coupled, A
V
= 1V/V Configuration
CLC5633
V
in
R
t
V
cm
0.1
μ
F
6.8
μ
F
+
V
CC
V
o
R
L
V
cm
Note:
R
and R
are tied to V
for minimum power
consumption and maximum output swing.
Channel 2 and 3 not shown.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
DS015005-40
FIGURE 2. DC Coupled, A
V
= +1V/V Configuration
CLC5633
V
in
R
t
V
cm
0.1
μ
F
6.8
μ
F
+
V
CC
V
o
R
L
V
cm
Note:
R
and R
and R
are tied to V
for minimum power
consumption and maximum output swing.
Channel 2 and 3 not shown.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+
-
1k
1k
+
-
1k
1k
+
-
1k
1k
V
cm
DS015005-41
FIGURE 3. DC Coupled, A
V
= +2V/V Configuration
C
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