
Application Division
(Continued)
Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance.
Minimize all trace lengths to reduce series inductances.
Use flush-mount printed circuit board pins for prototyping,
never use high profile DIP sockets.
Evaluation Board Information
A data sheet is available for the CLC730038/CLC730036
evaluation boards. The evaluation board data sheets pro-
vide:
Evaluation board schematics
Evaluation board layouts
General information about the boards
The evaluation boards are designed to accommodate dual
supplies. The boards can be modified to provide single
supply operation. For best performance; 1) do not connect
the unused supply, 2) ground the unused supply pin.
Special
Evaluation
Board
CLC5632
To optimize off-isolation of the CLC5632, cut the R
f
trace on
both the CLC730038 and the CLC730036 evaluation
boards. This cut minimizes capacitive feedthrough between
the input and the output. Figure 13 shows where to cut both
evaluation boards for improved off-isolation.
Considerations
for
the
SPICE Models
SPICE models provide a means to evaluate amplifier de-
signs. Free SPICE models are available for National’s mono-
lithic amplifiers that:
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise perfor-
mance
Support room temperature simulations
The
readme
file that accompanies the diskette lists released
models, and provides a list of modeled parameters. The
application note OA-18, Simulation SPICE Models for Na-
tional’s OpAmps, contains schematics and a reproduction of
the readme file.
Application Circuits
Single Supply Cable Driver
Figure 14 below shows the CLC5632 driving 10m of 75
coaxial cable. The CLC5632 is set for a gain of +2V/V to
compensate for the divide-by-two voltage drop at V
O
. The
response after 10m of cable is illustrated in Figure 15
DS015003-61
DS015003-52
FIGURE 13. Evaluation Board Changes
C
www.national.com
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