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參數(shù)資料
| 型號(hào)： | CLC5632IM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Dual, High Output, Programmable Gain Buffer |
| 中文描述： | DUAL BUFFER AMPLIFIER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 352K |
| 代理商： | CLC5632IM |
Application Division
(Continued)
Load Termination
The CLC5632 can source and sink near equal amounts of
current. For optimum performance, the load should be tied to
V
CM
.
Driving Cables and Capacitive Loads
When driving cables, double termination is used to prevent
reflections. For capacitive load applications, a small series
resistor at the output of the CLC5632 will improve stability
and settling performance. The
Frequency Response vs. C
L
plot, shown below in Figure 10 gives the recommended
series resistance value for optimum flatness at various ca-
pacitive loads.
Transmission Line Matching
One method for matching the characteristic impedance (Z
)
of a transmission line or cable is to place the appropriate
resistor at the input or output of the amplifier. Figure 11
shows typical inverting and non-inverting circuit configura-
tions for matching transmission lines.
Non-Inverting gain applications:
Connect pin 2 as indicated in the table in the
Closed
Loop Gain Selection
section.
Make R
1
, R
2
, R
6
, and R
7
equal to Z
O
.
Use R
3
to isolate the amplifier from reactive loading
caused by the transmission line, or by parasitics.
Inverting gain applications:
Connect R
3
directly to ground.
Make the resistors R
4
, R
6
, and R
7
equal to Z
O
.
Make R
5
\
R
g
= Z
O
.
The input and output matching resistors attenuate the signal
by a factor of 2, therefore additional gain is needed. Use C6
to match the output transmission line over a greater fre-
quency range. C6 compensates for the increase of the am-
plifier’s output impedance with frequency.
Power Dissipation
Follow these steps to determine the power consumption of
the CLC5632:
1. Calculate the quiescent (no-load) power: P
amp
= I
CC
(V
CC
V
EE
)
2. Calculate the RMS power at the output stage: P
= (V
V
) (I
), where V
and I
load
are the RMS voltage and
current across the external load.
3. Calculate the total RMS power: P
t
= P
amp
+P
O
The maxi-
mum power that the DIP and SOIC, packages can dissipate
at a given temperature is illustrated in Figure 12 The power
derating curve for any CLC5632 package can be derived by
utilizing the following equation:
where
T
amb
= Ambient temperature (C)
θ
= Thermal resistance, from junction to ambient, for a
given package (C/W)
Layout Considerations
A proper printed circuit layout is essential for achieving high
frequency performance. National provides evaluation boards
for the CLC5632 (CLC730038-DIP, CLC730036-SOIC) and
suggests their use as a guide for high frequency layout and
as an aid for device testing and characterization.
General layout and supply bypassing play major roles in high
frequency performance. Follow the steps below as a basis
for high frequency layout:
Include 6.8μF tantalum and 0.1μF ceramic capacitors on
both supplies.
Place the 6.8μF capacitors within 0.75 inches of the
power pins.
Place the 0.1μF capacitors less than 0.1 inches from the
power pins.
DS015003-48
FIGURE 10. Frequency Response vs. C
L
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5632
Z
0
R
6
V
o
Z
0
R
4
R
5
+
R
3
Z
0
R
1
R
2
V
1
V
2
+
C
6
R
7
Note:
Channel 2 not shown.
DS015003-49
FIGURE 11. Transmission Line Matching
DS015003-51
FIGURE 12. Power Derating Curve
C
www.national.com
14
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相關(guān)代理商/技術(shù)參數(shù) |
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| CLC5632IMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual, High Output, Programmable Gain Buffer |
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| CLC5632N WAF | 制造商:Texas Instruments 功能描述: |
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