參數(shù)資料
型號(hào)： CLC5632IM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Dual, High Output, Programmable Gain Buffer
中文描述： DUAL BUFFER AMPLIFIER, PDSO8
封裝： SOIC-8
文件頁(yè)數(shù)： 12/19頁(yè)
文件大?。?/td> 352K
代理商： CLC5632IM
Application Division
(Continued)
The denominator of Equation 1 is approximately equal to 1 at
low frequencies. Near the 3dB corner frequency, the inter-
action between R
and Z(j
ω
) dominates the circuit perfor-
mance. The value of the feedback resistor has a large affect
on the circuits performance. Increasing R
f
has the following
affects:
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
CLC5632 Design Information
Closed Loop Gain Selection
The CLC5632 is a current feedback op amp with R
= R
=
1k
on chip (in the package). Select from three closed loop
gains without using any external gain or feedback resistors.
Implement gains of +2, +1, and 1V/V by connecting pins 2
and 3 (or 5 and 6) as described in the chart below.
Z(j
ω
)/R
f
is the loop gain
Gain A
V
Input Connections
Non-Inverting (pins 3, 5)
ground
input signal
input signal
The gain accuracy of the CLC5632 is excellent and stable
over temperature change. The internal gain setting resistors,
R
and R
are diffused silicon resistors with a process varia-
tion of
±
20% and a temperature coefficient of - 2000ppm/C.
Although their absolute values change with processing and
temperature, their ratio (R
/R
) remains constant. If an exter-
nal resistor is used in series with R
g
, gain accuracy over
temperature will suffer.
Single Supply Operation (V
CC
= +5V, V
EE
= GND)
The specifications given in the
+5V Electrical Characteris-
tics
table for single supply operation are measured with a
common mode voltage (V
) of 2.5V. V
is the voltage
around which the inputs are applied and the output voltages
are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5632 is typically +0.8V to
+4.2V. The typical output range with R
L
= 100
is +1.0V to
+4.0V.
For single supply DC coupled operation, keep input signal
levels above 0.8V DC, AC coupling and level shifting the
signal are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in the
following 2 sections.
Inverting (pins 2, 6)
input signal
NC (open)
ground
1V/V
+1V/V
+2V/V
DC Coupled Single Supply Operation
Figure 1 Figure 2 and Figure 3 on the following page, show
the recommended configurations for input signals that re-
main above 0.8V DC.
DS015003-39
FIGURE 1. DC Coupled, A
V
= 1V/V Configuration
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5632
V
o
R
L
V
cm
0.1
μ
F
6.8
μ
F
+
V
in
R
t
V
cm
V
CC
R
t
and R
L
are tied to V
cm
for minimum power
Note:
Channel 2 not shown.
DS015003-40
FIGURE 2. DC Coupled, A
V
= +1V/V Configuration
1
7
6
8
5
3
4
2
1k
+
-
+
-
1k
1k
1k
CLC5632
V
o
R
L
V
cm
0.1
μ
F
6.8
μ
F
+
V
in
R
t
V
cm
V
CC
R
t
, R
L
and R
g
are tied to V
cm
for minimum power
Note:
Channel 2 not shown.
V
cm
DS015003-41
FIGURE 3. DC Coupled, A
V
= +2V/V Configuration
C
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLC5632IMX 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual, High Output, Programmable Gain Buffer
CLC5632IN 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual, High Output, Programmable Gain Buffer
CLC5632M/N WAF 制造商:Texas Instruments 功能描述:
CLC5632N WAF 制造商:Texas Instruments 功能描述:
CLC5632N/M WAF 制造商:Texas Instruments 功能描述:
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