參數(shù)資料
型號(hào): CLC533
廠商: National Semiconductor Corporation
英文描述: High-Speed 4:1 Analog Multiplexer
中文描述: 高速4:1模擬多路復(fù)用器
文件頁(yè)數(shù): 5/9頁(yè)
文件大小: 1306K
代理商: CLC533
5
http://www.national.com
positive supply voltage (+V
cc
)
negative supply voltage (-V
ee
)
differential voltage between any two GND’s
analog input voltage range
A
X
input voltage range (TTL mode)
A
X
input voltage range (ECL mode)
C
COMP
range
5pF to 100pF
thermal data
θ
jc
(°C/W)
16-pin plastic
50
16-pin Cerdip
20
16-pin SOIC
60
20-terminal LCC
20
16-pin side brazed
20
+5.0V
-5.2V
10mV
±2V
0V to +5.0V
0V to -2.0V
θ
ja
(°C/W)
60
65
75
35
50
positive supply voltage (+V
cc
)
negative supply voltage (-V
ee
)
differential voltage between any two GND’s
analog input voltage range
digital input voltage range
output short circuit duration (shorted to GND)
junction temperature
operating temperature range
CLC533AJP/AJE/AIB
storage temperature range
lead solder duration (+300°C)
ESD rating (human body model)
-0.5V to +7.0V
+0.5V to -7.0V
200mV
-V
ee
to +V
cc
-V
ee
to +V
cc
Infinite
+150°C
-40°C to +85°C
-65°C to +150°C
10 sec
<500V
Recommended Operating Conditions
Absolute Maximum Ratings
3
Note 1
: Test levels are as follows:
*
AJ : 100% tested at +25°C.
Note 2:
Settling time measured from the 50% analog output
transition.
Note 3:
Absolute maximum ratings are limiting values, to be
applied individually, and beyond which the serviceability of the cir-
cuit may be impaired. Functional operability under any of these
conditions is not necessarily implied. Exposure to maximum rat-
ings for extended periods may affect device reliability.
System Timing Diagram
Switching Transient Timing Diagram
APPLICATIONS INFORMATION
Operation
The CLC533 is a 4:1 analog multiplexer designed with a
closed loop architecture to provide very low harmonic
distortion and superior channel to channel isolation. This
low distortion, coupled with very fast switching
speed make the CLC533 an ideal multiplexer for data
conversion applications.
User selectable ECL or TTL
select logic adds to the versatility of this device. External
frequency
response
compensation
performance of the CLC533 to be optimized for each
application.
allows
the
Digital Interface and Channel Select
The CLC533 has two channel select pins which can be
used to select any one of the four inputs.
digital inputs can be configured to meet TTL, ECL or
CMOS logic levels with the D
REF
pin.
These
If D
REF
is left
open, then the A
0
and A
1
select inputs will respond to
ECL 10K switching levels (Figure 1). For TTL or CMOS
levels, D
REF
should be tied to V
cc
(Figure 2). There is an
internal series resistor which makes it possible to
connect D
REF
directly to the power supply. Select pins
according to the truth table shown on the front page. A
more positive voltage is considered to be a logic ‘1’.
Therefore with no connection to A
0
or A
1
the internal pull-
up resistors will select the D input to be passed through
to the output.
Compensation
The CLC533 is externally compensated, allowing
the user to select the bandwidth that best suits
the application. Decreasing bandwidth has two
advantages: lower noise and lower switching tran-
sients. In a sampled system, noise at frequencies
Package Thermal Resistance
Package
AJP
AJE
CERDIP
θ
JC
θ
JA
45°C/W
35°C/W
25°C/W
95°C/W
100°C/W
65°C/W
Reliability Information
Transistor count
144
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