- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379896 > CLC503 (National Semiconductor Corporation) Comlinear CLC503 180MHz, Differential-Output Amplifier PDF資料下載
參數(shù)資料
| 型號(hào)： | CLC503 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Comlinear CLC503 180MHz, Differential-Output Amplifier |
| 中文描述： | Comlinear CLC503 180Mhz的，差分輸出放大器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 100K |
| 代理商： | CLC503 |
I
Pin 1
Power Down (P
DN
):
The power down pin takes
CMOS input levels. Use this to decrease the
power from 250mW to 40mW. This is not a
signal disable pin. A CMOS gate will drive this
input. The quiescent supply current will be
decreased when P
DN
is at least 1V higher than
V
cm
. When the current is turned off, the output
voltage V
o
, will go to approximately 4.3V. An
internal pull down resistor of 10k allows P
DN
to
be left open when not used.
I
Pin 2
Input Voltage (V
in
):
This is the signal input. The
recommended input range is ±1V. The linear
operating range is approximately ±1.4V This
input controls the differential output voltage.
Because of the closed loop nature of the trans-
conductance stage, the transfer function is highly
linear. Refer to
Output Voltage
pin for output
signal limitations.
I
Pin 3
Ground (GND):
Tie to low impedance analog
ground.
I
Pins 4 and 5
Power Supplies (V
EE
and V
CC
):
For optimum
performance, use linear ±5V power supplies.
Use bypass capacitors of 0.1
μ
F and 6.8
μ
F on the
power supply lines to decrease any noise that
could be injected into the circuit by the power
supplies. Place the bypass capacitors as close
to the device pins as possible. Remove the
ground plane from the board underneath the
device to eliminate parasitic capacitance. Refer
to
Printed Circuit Board Layout
section for
more layout suggestions.
I
Pins 6 and 7
Output Voltage (-V
o
and +V
o
):
These are the
differential signal output pins. The output voltage
at these pins is limited to 0.7V to 3.9V. The
output recovery time after exceeding these limits
is approximately 40ns. The output voltage can
be defined as:
I
Pin 8
Common-Mode Voltage (V
cm
):
This input sets
the common-mode output operating points. The
common mode input voltage can range from 1.5V
to 3.5V. Refer to
Output Voltage
pin discussion
for limitations on the output range.
Load:
The CLC503 is intended to drive high speed
CMOS analog-to-digital converters, such as the
CLC949. Resistive loading will affect the gain and
common mode offset. It is not recommended to drive
resistive loads below 10k
with this part. See Figure 5
for gain vs. load with specified range in device output
resistance.
Figure 5: Gain vs. Resistive Load
Settling Time:
The CLC503 settles to 0.1% in 15ns
with a 5pF load, the input capacitance of the CLC949.
Refer to the
Settling Time vs. Capacitive Load
plot in
the
Typical Performance Characteristics
section.
Power Dissipation
To calculate the power dissipation, P
T
, for the CLC503,
use the following equation:
The performance of the CLC503 is strongly dependent
on proper layout, and adequate power supply
decoupling. The parasitic capacitance at the output of
the CLC503 and the input to the CLC949, or any other
analog-to-digital converter, must be kept to a minimum.
Consider the following guidelines:
I
Use a ground plane.
I
Bypass power supply pins with monolithic
capacitors of 0.1
μ
F and with 6.8
μ
F tantalum
capacitors. Place the capacitors less than 0.1"
(3mm) from the pin.
I
Remove the ground plane underneath the
device and 0.1" (3mm) from all input/output
pads.
Interfacing the CLC503 with the CLC949
The CLC503 can be easily interfaced with the CLC949
as shown in Figure 6. An evaluation board is available
for proto-typing and measurements.
P
I
V
V
T
CC
CC
EE
=
(
)
+V
-V
V
odiff
V
V
=
V
V
+V
+V
-V
-V
(
2V
V
2
V
o
cm
in
o
cm
in
(
o
o
in
ocm
o
o
cm
=
=
+
=
=
=
)
)
G
Load Resistance (
)
03 Fi
2
1.5
0
100
1000
10000
1
0.5
100000
2.5
R
o
= 600
= R
omax
R
o
= 400
= R
omin
Design Information
Printed Circuit Board Layout
5
http://www.national.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC503AJE | IC-SM-DIFF OUTPUT AMP |
| CLC505 | High-Speed, Programmable-Supply Current, Monolithic Op Amp |
| CLC505AJE | High-Speed, Programmable-Supply Current, Monolithic Op Amp |
| CLC505ALC | High-Speed, Programmable-Supply Current, Monolithic Op Amp |
| CLC520AJP | Amplifier with Voltage Controlled Gain, AGC+Amp |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC503AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IC-SM-DIFF OUTPUT AMP |
| CLC505 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Speed, Programmable-Supply Current, Monolithic Op Amp |
| CLC-505 | 制造商:Platt Luggage 功能描述: |
| CLC505 WAF | 制造商:Texas Instruments 功能描述: |
| CLC505AID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Feedback Operational Amplifier |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。