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參數(shù)資料
| 型號： | CLC503 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Comlinear CLC503 180MHz, Differential-Output Amplifier |
| 中文描述： | Comlinear CLC503 180Mhz的，差分輸出放大器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 100K |
| 代理商： | CLC503 |
CLC503 APPLICATIONS
APPLICATION CONSIDERATIONS
Theory of Operation
Figure 1 is a simplified schematic of the CLC503.
Figure 1: Simplified Block Diagram
The input voltage drives a unity gain buffer, B
1
, and
an inverting buffer, B
2
. These buffers drive emitter
followers, Q
1
and Q
2
. Resistor, R
3
, is the gain set
resistor. The combination of B
1
, B
2
, Q
1
, Q
2
and R
3
form a transconductance stage. The input voltage
across R
3
is converted to an in-phase and out-of-
phase current through the collectors of Q
1
and Q
2
. The
current through R
3
is:
The common mode voltage across R
4
is converted
to a current. Transistor Q
5
has a collector current
equal to:
V
V
V
R
4
The common mode current is scaled and mirrored back
to Q
1
and Q
2
. These currents, I, are converted back to
a voltage at the collector load resistors, R
1
and R
2
.
This forms the common-mode output voltage.
V
ocm
= V
CC
– V
diode
– R
1
I
I = 16I
cm
V
ocm
= V
cm
Figure 2 depicts the differential output voltage limits of
the CLC503.
Figure 2: Differential Output Voltage
Centered around V
cm
, the outputs are derived from the
following equations.
The input to output relationship is shown in Figure 3.
V
in
V
odiff
±1V
2V
pp
±2V
4V
pp
±1.4V max
±2.8V max
Figure 3: Input vs. Output Relationship
Pulling the power down line (P
DN
) high decreases the
quiescent supply current. This turns off the current
flowing in Q
5
, and therefore Q
1
and Q
2
, allowing the
output voltages to drift high, to approximately 4.3V.
Since the signal is not significantly attenuated, P
DN
does not effectively isolate the input from the output.
This part is not recommended for use as a multiplexer.
Refer to
Pin Descriptions - Power Down pin
-
section. No damage occurs to the device when P
DN
is
high and the input is driven to the supply voltage.
Pin Descriptions
Figure 4: CLC503 Functional Pin Descriptions
4
+1
-V
o
+V
in
B1
Q
1
R
1
V
CC
R
3
I
-1
+V
o
B2
Q
2
R
2
I
R
4
I
cm
Q
5
Q
4
Q
4
V
EE
P
DN
V
cm
I
3
Current Mirror
R
1
= R
2
2 R
1
= R
3
R
4
= 16R
1
O
Input Voltage (V)
3.7
0.8
-1
0
1
2.25
3.25V
1.25V
V
cm
+V
o
= V
cm
+V
in
-V
o
= V
cm
-V
in
+V
o
V
in
P
DN
2
3
1
7
V
CC
5
-V
o
6
V
cm
8
V
EE
4
I
2V
R
=
=
V
I R
I R
)
R
R
V
I 2R
V
2V
R
2V
2R
2R
R
V
3
in
3
odiff
2
1
2
odiff
1
(
odiff
in
3
1
1
3
odiff
in
=
+
=
=
)
=
=
I
R
16R
cm
CC
cm
diode
4
1
≈
=
+V
V
V
-V
V
V
V
+V
-V
2V
o
cm
in
o
cm
in
odiff
o
o
in
=
+
=
=
=
– (
)
I
V
V
R
V
CC
cm
diode
1
=
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