
Figure 6
Positive Peak Detector
The CLC428's dual amplifiers can be used to implement a
unity-gain peak detector circuit as shown in Figure 7.
Figure 7
The acquisition speed of this circuit is limited by the
dynamic resistance of the diode when charging C
hold
. A
plot of the of the circuit's performance is shown in Figure
8 with a 1MHz sinusoidal input.
Figure 8
A current source, built around Q
1
, provides the necessary
bias current for the second amplifier and prevents satura-
tion when power is applied. The resistor, R, closes the loop
while diode D
2
prevents negative saturation when V
in
is
less than V
c
. A MOS-type switch (not shown) can be used
to reset the capacitor's voltage.
The maximum speed of detection is limited by the delay
of the op amps and the diodes. The use of Schottky diodes
will provide faster response.
Adjustable or Bandpass Equalizer
A "boost" equalizer can be made with the CLC428 by
summing a bandpass response with the input signal, as
shown in Figure 9.
Figure 9
The overall transfer function is shown in Eq. 5.
V
V
R
K R
R
s2Q
ω
s
sQ
1
out
in
b
+
a
b
o
+
2
o
o
2
=
F
I
+
h
ω
ω
Eq. 5
To build a boost circuit, use the design equations Eq. 6 and
Eq. 7.
R C
2
Q, 2C R ||R
o
ω
1
ω
Q
a
b
o
=
=
h
Eq. 6,7
Select R
2
and C using Eq. 6. Use reasonable values for
high frequency circuits - R
2
between 10
and 5k
, C
between 10pF and 2000pF. Use Eq. 7 to determine the
parallel combination of R
a
and R
b
. Select R
a
and R
b
by
either the 10
to 5k
criteria or by other requirements
based on the impedance V
in
is capable of driving. Finish
the design by determining the value of K from Eq. 8.
Peak Gain
V
V
R
KR
2
out
in
o
a
=
=
ω
c h
2
1
Eq. 8
Figure 10 shows an example of the response of the circuit
of Figure 9, where f
o
is 2.3MHz. The component values
are as follows: R
a
=2.1k
, R
b
=68.5
, R
2
=4.22k
, R
=500
, KR =50
, C =120pF.
Figure 10
Q
1
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