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參數(shù)資料
| 型號： | CLC418 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual High-Speed, Low-Power Line Driver |
| 中文描述： | 雙高速，低功耗，線路驅(qū)動器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 280K |
| 代理商： | CLC418 |
http://www.national.com
8
Thermal Design
To calculate the power dissipation for the CLC418, follow
these steps for each individual amplifier:
1) Calculate the no-load op amp power:
P
amp
= I
CC
(V
CC
– V
EE
)
2) Calculate the output stage’s RMS power:
P
o
= (V
CC
– V
load
)
I
load
, where V
load
and I
load
are the RMS voltage and current across the
external load
3) Calculate the total op amp RMS power:
P
t
= P
amp
+ P
o
Now calculate the total power dissipated in the package:
4) Sum P
t
for both op amps to obtain P
tot
To calculate the maximum allowable ambient tempera-
ture, solve the following equation: T
amb
= 175 – P
tot
θ
JA
,
where
θ
JA
is the thermal resistance from junction
to ambient in °C/W, and T
amb
is in °C. The
Package
Thermal Resistance
section contains the thermal
resistance for various packages.
Dynamic Range (input /output protection)
ESD diodes are present on all connected pins for protec-
tion from static voltage damage. For a signal that may
exceed the supply voltages, we recommend using diode
clamps at the amplifier’s input to limit the signals to less
than the supply voltages.
The CLC418’s output current can exceed the maximum
safe output current. To limit the output current to < 96mA:
I
Limit the output voltage swing with diode
clamps at the input
I
Make sure that R
V
o(max)
is the output voltage swing limit, and I
o(max)
is the
maximum safe output current.
Dynamic Range (input /output levels)
The
Electrical Characteristics
section specifies the
Common-Mode Input Range and Output Voltage
Range; these voltage ranges scale with the supplies.
Output Current is also specified in the
Electrical
Characteristics
section.
Unity gain applications are limited by the Common-Mode
Input Range. At greater non-inverting gains, the Output
Voltage Range becomes the limiting factor. Inverting
gain applications are limited by the Output Voltage
Range (and by the previous amplifier’s ability to drive
R
g
). For transimpedance gain applications, the sum of
the input currents injected at the inverting input pin of
the op amp needs to be:
, where V
max
is the
Output Voltage Range (see the
DC Gain (transimpedance)
sub-section for details).
The equivalent output load needs to be large enough
so that the minimum output current can produce the
required output voltage swing. See the
DC Design
(output loading)
sub-section for details.
Dynamic Range (noise)
The output noise defines the lower end of the CLC418’s
useful dynamic range. Reduce the value of resistors in
the circuit to reduce noise.
See the App Note
Noise Design of CFB Op Amp
Circuits
for more details. Our SPICE models support noise
simulations.
Dynamic Range (distortion)
The distortion plots in the
Typical Performance
Characteristics
section show distortion as a function
of load resistance, frequency, and output amplitude.
Distortion places an upper limit on the CLC418’s
dynamic range.
The CLC418’s output stage combines a voltage buffer
with a complementary common emitter current source.
The interaction between the buffer and the current
source produces a small amount of crossover distortion.
This distortion mechanism dominates at low output swing
and low resistance loads. To avoid this type of distortion,
use the CLC418 at high output swing.
Realized output distortion is highly dependent upon the
external circuit. Some of the common external circuit
choices that can improve distortion are:
I
Short and equal return paths from the load to
the supplies
I
De-coupling capacitors of the correct value
I
Higher load resistance
Printed Circuit Board Layout
High frequency op amp performance is strongly dependent
on proper layout, proper resistive termination and
adequate power supply decoupling. The most important
layout points to follow are:
I
Use a ground plane
I
Bypass power supply pins with:
I
monolithic capacitors of about 0.1
μ
F place
less than 0.1” (3mm) from the pin
I
tantalum capacitors of about 6.8
μ
F for
large signal current swings or improved
power supply noise rejection;
we recommend a minimum of 2.2
μ
F
for any circuit
I
Minimize trace and lead lengths for components
between the inverting and output pins
I
Remove ground plane 0.1” (3mm) from all
input/output pads
I
For prototyping, use flush-mount printed circuit
board pins;
never use high profile DIP sockets
.
Evaluation Board
Separate evaluation boards are available for proto-typing
and measurements. Additional information is available in
the evaluation board literature.
V
I
L
o(max)
o(max)
≥
I
V
R
in
max
f
≤
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PDF描述 |
|---|---|
| CLC418AJ | Dual High-Speed, Low-Power Line Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
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| CLC418AJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual High-Speed, Low-Power Line Driver |
| CLC420 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Speed, Voltage Feedback Op Amp |
| CLC420AE-QML | 制造商:Rochester Electronics LLC 功能描述:HI SPEED VOLTAGE FEEDBK OP AMP - Bulk 制造商:Texas Instruments 功能描述: |
| CLC420AIB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| CLC420AID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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