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參數(shù)資料
| 型號(hào)： | CLC418 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual High-Speed, Low-Power Line Driver |
| 中文描述： | 雙高速，低功耗，線路驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | CLC418 |
http://www.national.com
6
Figure 2: Inverting Gain
Select R
g
to set the DC gain:
. At large gains,
R
g
becomes small and will load the previous stage. This
can be solved by driving R
g
with a low impedance buffer
like the CLC111, or increasing R
f
and R
g
. See the
AC Design (small signal bandwidth)
sub-section for
the tradeoffs.
DC gain accuracy is usually limited by the tolerance of R
f
and R
g
.
DC Gain (transimpedance)
Figure 3 shows a transimpedance circuit where the
current I
in
is injected at the inverting node. The current
source’s output resistance is much greater than R
f
.
The DC transimpedance gain is:
The recommended R
f
is 3k
. Parasitic capacitance at
the inverting node may require a slight increase of R
f
to
maintain a flat frequency response.
DC gain accuracy is usually limited by the tolerance of R
f
.
Figure 3: Transimpedance Gain
DC Design (level shifting)
Figure 4 shows a DC level shifting circuit for inverting
gain configurations. V
ref
produces a DC output level shift
R
R
ref
of
which is independent of the DC output
produced by V
in
.
Figure 4: Level Shifting Circuit
DC Design (DC offsets)
The DC offset model shown in Fig. 5 is used to calculate
the output offset voltage. The equation for output offset
voltage is:
(
The current offset terms, I
BN
and I
BI
,
do not track
each other
. The specifications are stated in terms of
magnitude only. Therefore, the terms V
os
, I
BN
, and I
BI
can have either polarity. Matching the equivalent
resistance seen at both input pins does not reduce the
output offset voltage.
Figure 5: DC Offset Model
DC Design (output loading)
R
L
, R
f
, and R
g
load the op amp output. The equivalent
load seen by the output in Figure 5 is:
{
R
L(eq)
=
R
L
|| (R
f
+ R
eq2
), non-inverting gain
R
L
|| R
f
, inverting and transimpedance gain
The equivalent output load (R
L(eq)
) needs to be large
enough so that the output current can produce the
required output voltage swing.
AC Design (small signal bandwidth)
The CLC418 current-feedback amplifier bandwidth is a
function of the feedback resistor (R
f
), not of the DC voltage
gain (A
V
). The bandwidth is approximately proportional
1
R
f
to
As a rule, if R
f
doubles, the bandwidth is cut in half.
Other AC specifications will also be degraded.
Decreasing R
f
from the recommended value increases
peaking, and
for very small values of R
f
oscillation
will occur.
AC Design (minimum slew rate)
Slew rate influences the bandwidth of large signal
sinusoids. To determine an approximate value of slew
rate necessary to support a large sinusoid, use the
R
R
A
g
f
v
=
A
V
I
in
R
R
o
f
=
=
+
-
C1/2
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
CC
0.1
μ
F
6.8
μ
F
V
EE
R
t
3(5)
2(6)
4
8
1(7)
+
I
in
V
in
R
g
+
-
C1/2
418 Fig4
R
f
V
o
V
ref
R
ref
R
t
V
,
ref
f
V
V
I
R
1
R
R
I
R
o
os
BN
eq1
f
eq2
BI
f
=
+
)
+
+
(
)
R
eq1
R
f
+
-
R
eq2
C1/2
I
BI
I
BN
V
os
-
V
o
R
L
+
.
+
-
C1/2
418 Fig2
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
V
CC
0.1
μ
F
6.8
μ
F
V
EE
R
g
R
t
3(5)
2(6)
4
8
1(7)
+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC418AJ | Dual High-Speed, Low-Power Line Driver |
| CLC420AJP | High-Speed, Voltage Feedback Op Amp |
| CLC420AJE | High-Speed, Voltage Feedback Op Amp |
| CLC420 | High-Speed, Voltage Feedback Op Amp |
| CLC420AJE-TR13 | High-Speed, Voltage Feedback Op Amp |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC418AJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual High-Speed, Low-Power Line Driver |
| CLC420 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Speed, Voltage Feedback Op Amp |
| CLC420AE-QML | 制造商:Rochester Electronics LLC 功能描述:HI SPEED VOLTAGE FEEDBK OP AMP - Bulk 制造商:Texas Instruments 功能描述: |
| CLC420AIB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| CLC420AID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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