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參數(shù)資料
| 型號： | CLC417AJE |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Dual Low-Power, Programmable Gain Buffer |
| 中文描述： | DUAL BUFFER AMPLIFIER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 147K |
| 代理商： | CLC417AJE |
5
http://www.national.com
Channel Matching
Channel matching and crosstalk efficiency are largely
dependent on board layout. The layout of National’s dual
amplifier evaluation boards are optimized to produce
maximum channel matching and isolation. Typical
channel matching for the CLC417 is shown in Figure 3.
Figure 3: Channel Matching
The CLC417’s channel-to-channel isolation is better than
70dB for input frequencies of 4MHz. Input referred
crosstalk vs. frequency is illustrated in Figure 4.
Figure 4: Input Referred Crosstalk vs. Frequency
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC417 will
improve stability. The
R
s
vs. Capacitive Load
plot, in the
Typical Performance
section, gives the
recommended series resistance value for optimum
flatness at various capacitive loads.
Power Dissipation
The power dissipation of an amplifier can be described in
two conditions:
I
Quiescent Power Dissipation -
P
Q
(No Load Condition)
I
Total Power Dissipation -
P
T
(with Load Condition)
The following steps can be taken to determine the power
consumption for each CLC417 amplifier:
1. Determine the quiescent power
P
Q
= (V
CC
- V
EE
)
I
CC
2. Determine the RMS power at the output stage
P
O
= (V
CC
- V
load
) (I
load
), where V
load
and I
load
are the RMS voltage and current across the
external load.
3. Determine the total RMS power
P
T
= P
Q
+ P
O
Add the total RMS powers for both channels to determine
the power dissipated by the dual.
The maximum power that the package can dissipate at a
given temperature is illustrated in the
Power Derating
curves in the
Typical Performance
section. The power
derating curve for any package can be derived by utiliz-
ing the following equation:
where: T
amb
= Ambient temperature (°C)
θ
JA
= Thermal resistance, from junction to
ambient, for a given package (°C/W)
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC417 (CLC730038 - DIP,
CLC730036 - SOIC) and suggests their use as a guide
for high frequency layout and as an aid for device testing
and characterization.
Supply bypassing is required for best performance. The
bypass capacitors provide a low impedance return
current path at the supply pins. They also provide high
frequency filtering on the power supply traces. Other
layout factors play a major role in high frequency
performance. The following are recommended as a basis
for high frequency layout:
1. Include 6.8
μ
F tantalum and 0.1
μ
capacitors on both supplies.
2. Place the 6.8
μ
F capacitors within 0.75 inches
of the power pins.
3. Place the 0.1
μ
F capacitors less than 0.1
inches from the power pins.
4. Remove the ground plane near the input
and output pins to reduce parasitic
capacitance.
5. Minimize all trace lengths to reduce series
inductances.
Additional information is included in the evaluation board
literature.
Special Evaluation Board Considerations
To optimize off-isolation of the CLC417, cut the R
f
trace
on both the 730038 and 730036 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and output. Figure 5 indicates the alterations
recommended to improve off-isolation.
M
Frequency (MHz)
1
10
100
A
= +2
R
L
= 100
V
o
= 2V
pp
P
-450
-360
-270
-180
-90
0
Channel A
Channel A
Channel B
Channel B
C
Frequency (MHz)
-120
-100
-80
-60
-40
-20
1
100
10
P
(175
Tamb)
JA
=
°
θ
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PDF描述 |
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| CLC417AJP | Dual Low-Power, Programmable Gain Buffer |
| CLC418 | Dual High-Speed, Low-Power Line Driver |
| CLC418AJ | Dual High-Speed, Low-Power Line Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC417AJP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Low-Power, Programmable Gain Buffer |
| CLC418 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual High-Speed, Low-Power Line Driver |
| CLC418AJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual High-Speed, Low-Power Line Driver |
| CLC420 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Speed, Voltage Feedback Op Amp |
| CLC420AE-QML | 制造商:Rochester Electronics LLC 功能描述:HI SPEED VOLTAGE FEEDBK OP AMP - Bulk 制造商:Texas Instruments 功能描述: |
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