參數(shù)資料
型號: CLC417AJE
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運動控制電子
英文描述: Dual Low-Power, Programmable Gain Buffer
中文描述: DUAL BUFFER AMPLIFIER, PDSO8
封裝: SOIC-8
文件頁數(shù): 4/8頁
文件大小: 147K
代理商: CLC417AJE
http://www.national.com
4
CLC417 Typical Performance Characteristics
(V
cc
= ±5V, A
v
= +2, R
L
= 100
; unless specified)
CLC417 OPERATION
Description
The CLC417 is a dual current feedback buffer with the
following features:
I
Gains of +1, -1, and 2 are achievable without
external resistors
I
Differential gain and phase errors of 0.01%
and 0.03° into a 150
load
I
Low, 3.9mA, supply current per amplifier
The convenient 8-pin package and internal resistors
make common applications, like that seen on the front
page, easily feasible in a limited amount of space. The
professional video quality differential gain and phase
errors and low power capabilities of the CLC417 make
this product a good choice for video applications.
If gains other than +1, -1, or +2V/V are required, then the
CLC416 can be used. The CLC416 is a dual current
feedback amplifier with near identical performance, and
allows for external feedback and gain resistors.
Closed Loop Gain Selection
Gains of +1, +2, and -1V/V can be achieved by both of
the CLC417’s amplifiers. Implement the gain selection
by connecting the inverting (-IN) and non-inverting (+IN)
pins as described in the table below.
The gain accuracy of the CLC417 is excellent and
stable over temperature. The internal feedback and gain
setting resistors, R
f
and R
g
, are diffused silicon resistors.
R
f
and R
g
have a process variation of ±20% and a
temperature coefficient of ~ 2000ppm/°C. Although the
absolute values of R
f
and R
g
change with processing and
temperature, their ratio (R
f
/R
g
) remains constant. If an
external resistor is used in series with R
g
, gain accuracy
over temperature will be impacted by temperature coeffi-
cient differences between internal and external resistors.
Non-Inverting Unity Gain Considerations
Gains of +1V/V are obtained by removing all resistive
and capacitive connections between the inverting
pins and ground on the CLC417 amplifiers. Too much
capacitive coupling between the inverting pin and ground
may cause stability problems. Minimize this capacitive
coupling by removing the ground plane near the
input and output pins. The response labeled
open
in
Figure 1 is the result of the inverting pin left open and all
capacitive coupling removed. A flatter response can be
obtained by inserting a resistor between the
inverting and non-inverting pins as shown in Figure 2.
The two remaining plots in Figure 1 illustrate a 300
resistor and a short connected between pins 2 and 3 of
the CLC417.
Figure 1: Frequency Response vs.
Unity Gain Configuration
Figure 2: Optional Unity Gain Configuration
PSRR and CMRR
P
10k
100k
1M
Frequency (Hz)
10M
100M
60
50
40
30
20
10
PSRR
CMRR
Typical DC Errors vs. Temperature
O
Temperature (
°
C)
6
5
4
1
-50
0
100
3
2
I
BN
B
μ
A
1
0
-1
-2
-3
50
I
BI
V
IO
Power Derating Curves
P
Ambient Temperature (
°
C)
0.8
1.0
0.6
0
0
20
40
60
80
100
120
140
160
180
0.4
0.2
AJE
AJP
M
Frequency (MHz)
1
100
Short
10
Open
R = 300
250
+
-
+
-
250
250
250
SMA
Input1
R
in
50
R
SMA
Output1
R
out
50
NOTE:
The same technique can also
be applied to Channel B. Bypass
capacitors not shown.
Gain
A
v
Input Connections
+IN
ground
input signal
input signal
-IN
-1V/V
+1V/V
+2V/V
input signal
NC (open)
ground
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