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參數(shù)資料
| 型號： | CLC416AJ |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual Low-Power, 120MHz Op Amp |
| 中文描述： | 雙低功耗，120MHz的運算放大器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 167K |
| 代理商： | CLC416AJ |
CLC416 Typical Performance Characteristics
(V
cc
= ±5V, A
v
= +2, R
f
= 348
,
R
L
= 100
; unless specified)
Frequency Response
N
Frequency (MHz)
1
10
100
V
o
= 0.5V
pp
P
-90
-180
-450
-270
-360
0
v
= 1
R
f
A
v
= 2
R
f
A
v
= 4
R
f
A
A
R
f
= 10
Inverting Frequency Response
N
Frequency (MHz)
1
10
100
P
-270
-360
-630
-450
-540
-180
-90
0
A
R
f
= -1
V
o
= 0.5V
pp
A
R
f
= -4
A
R
f
= -10
A
R
f
= = -2
Frequency Response vs. R
L
M
Frequency (MHz)
1
10
100
P
-90
-180
-450
-270
-360
0
R
L
= 100
V
o
= 1V
pp
A
v
= +2
R
L
= 1k
R
L
= 50
R
L
= 50
R
L
= 100
R
L
= 1k
Frequency Response vs. V
out
M
Frequency (MHz)
1
10
100
1V
pp
A
v
= +2
0.2V
pp
2V
pp
5V
pp
Frequency Response vs. C
L
M
Frequency (MHz)
1
10
100
V
o
= 1V
pp
R
s
= 107
C
L
= 10pF
R
s
= 39.25
C
L
= 47pF
R
s
= 27.4
C
L
= 100pF
R
= 8
C
L
= 1000pF
R
s
1k
348
348
C
L
Open Loop Transimpedance Gain, Z(s)
2
o
/
i
|
)
1k
10M
100M
Frequency (Hz)
130
110
90
70
50
30
P
200
160
120
80
40
0
Gain
Phase
1M
100k
10k
100
-
+
CLC416
V
o
I
i
Maximum Output Voltage vs. R
L
M
Load (
)
0
100
200
300
400
-4
-2
0
2
4
500
600
Recommended R
s
vs. Capacitive Load
R
s
)
C
L
(pF)
0
20
40
60
80
100
120
10
100
1000
2nd & 3rd Harmonic Distoration
D
Frequency (MHz)
1
10
-70
-80
-90
-60
-50
-40
V
o
= 2V
pp
3rd, R
L
= 100
2nd, R
L
= 100
2nd, R
L
= 1k
3rd, R
L
= 1k
2nd Harmonic Distortion vs. P
out
D
Output Power (dBm)
-90
-85
-80
-75
-70
-65
-60
-55
-10
-5
0
5
10
1MHz
500kHz
5MHz
10MHz
50
348
348
50
P
o
3rd Harmonic Distortion vs. P
out
D
Output Power (dBm)
-100
-90
-80
-70
-60
-50
-40
-10
-5
0
5
10
1MHz
500kHz
5MHz
10MHz
50
348
348
50
P
o
Differential Gain & Phase
G
Number of 150
Loads
0
1
2
4
P
0
0.01
0.03
0.02
0.06
0.03
0.09
0.04
0.12
0.05
0.15
0.06
0.18
0.07
0.21
0.08
0.24
0.09
0.27
0.1
0.30
Phase Negative Sync
Phase Positive Sync
Gain Positive Sync
GainSync
3
Small Signal Pulse Response
O
Time (5ns/div)
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
A
v
= +1
A
v
= -1
Large Signal Pulse Response
O
Time (5ns/div)
-2
-1
0
1
2
A
v
= +2
A
v
= -2
PSRR and CMRR
P
10k
100k
1M
Frequency (Hz)
10M
100M
60
50
40
30
20
10
PSRR
CMRR
3
http://www.national.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC417 | Dual Low-Power, Programmable Gain Buffer |
| CLC417AJE | Dual Low-Power, Programmable Gain Buffer |
| CLC417AJP | Dual Low-Power, Programmable Gain Buffer |
| CLC418 | Dual High-Speed, Low-Power Line Driver |
| CLC418AJ | Dual High-Speed, Low-Power Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC416AJE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-SM-DUAL 110MHZ OP-AMP |
| CLC416AJP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-DUAL 110MHZ OP-AMP |
| CLC417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Low-Power, Programmable Gain Buffer |
| CLC417AJE | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Low-Power, Programmable Gain Buffer |
| CLC417AJP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Low-Power, Programmable Gain Buffer |
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