參數(shù)資料
型號: CLC406
廠商: National Semiconductor Corporation
英文描述: Wideband, Low Power Monolithic Op Amp(寬帶低功耗單片運算放大器)
中文描述: 寬帶,低功耗單片運算放大器(寬帶低功耗單片運算放大器)
文件頁數(shù): 9/11頁
文件大小: 292K
代理商: CLC406
Application Division
(Continued)
erally higher and relatively insensitive to gain setting for
inverting gain operation. An additional discussion of slew
rates can be found in the CLC404 data sheet.
As the output signal swing is increased, the slew enhance-
ment circuit found in the buffer stage acts to suppress har-
monic distortions. This is one reason the CLC406 does not
exhibit a simple relationship between output power and dis-
tortion. For example, the 2-tone, 3rd order spurious plot
shows the spurious level to remain nearly constant over test
tone power. For this reason the CLC406 does not exhibit an
intercept type performance where the relative spurious lev-
els change at twice the rate of the test tone power.
Differential Gain and Phase
Differential gain and phase performance specifications are
common to composite video distribution applications. These
specifications refer to the change in small signal gain and
phase of the color subcarrier frequency (4.43MHz for PAL
composite video) as the amplifier output is swept over a
range of DC voltages. For this test only, the CLC406 is
specified at a gain of +2 while connected to one or more
doubly terminated 75
loads. Application Note OA-08 pro-
vides an additional discussion of differential gain and phase
measurements.
Non-inverting Source Impedance
For best operation, the DC source impedance looking out of
the non-inverting input should be less than 3k
but greater
than 20
. Parasitic self oscillations may occur in the input
transistors if the DC source impedance is out of this range.
This impedance also acts as the gain for the non-inverting
input bias and noise currents and therefore can become
troublesome for high values of DC source impedance. The
inverting configuration of Figure 2 shows a 25
resistor to
ground on the non-inverting input which insures stability but
does not provide bias current cancellation. The input bias
currents are unrelated for a current feedback amplifier which
eliminates the need for source impedance matching to
achieve bias current cancellation.
DC Accuracy and Noise
Equation 1 shows and example of the output offset voltage
computation. The calculation is developed using typical bias
current and offset voltage specifications at 25C, a gain (Av)
of +6 and a non-inverting source impedance (R
s
) of 25
.
Equation 1: Output Offset Voltage Calculation
Output Offset Voltage V
=(
±
I
R
±
V
io
)(1+R
/R
)
±
I
bi
R
f
V
O
=(
±
5μA(25
)
±
2mV)(6)
±
3μA(500
)=
±
14.25mV
Improved output offset voltage is possible using the compos-
ite circuits shown in Application Note OA-07.
The total output spot noise is computed in a similar fashion
to the output offset voltage. Using the input spot noise volt-
age and the two input spot noise currents, the total output
spot noise is developed through the same gain equations for
each term but combined as the square root of the sum of
squared contributing elements. Application Note OA-12 pro-
vides a more detailed discussion of noise calculations for
current feedback amplifiers.
Printed Circuit Layout
As with any high speed component, a careful attention to the
board layout is necessary for optimum performance. Of par-
ticular importance is the careful control of parasitic capaci-
tances on the output pin. As the output impedance plot
shows, the closed loop output of the CLC406 eventually
becomes inductive as the loop gain rolls off with increasing
frequency. Direct capacitive loading on the output pin can
quickly lead to peaking in the frequency response, overshoot
in the pulse response, ringing or even sustained oscillations.
The “Suggested Series R
s
vs. C” plot should be used as a
starting point when a capacitive load must be driven.
Evaluation boards (CLC730013-DIP,CLC730027-SOIC, and
CLC730068-SOT) for the CLC406 are available. Further
layout suggestions can be found in Application Note OA-15.
C
www.national.com
9
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