
Input - Bias Current, Impedances, and Source
Termination Considerations
The CLC405 has:
a 6M
non-inverting input impedance.
a 100nA non-inverting input bias current.
If a large source impedance application is considered,
remove all parasitic capacitance around the non-invert-
ing input and source traces.
near the input and source act as a low-pass filter and
reduce bandwidth.
Parasitic capacitances
Current feedback op amps have uncorrelated input
bias currents.These uncorrelated bias currents prevent
source impedance matching on each input from can-
celing offsets. Refer to application note OA-07 of the
data book to find specific circuits to correct DC offsets.
Layout Considerations
Whenever questions about layout arise, USE THE
EVALUATION BOARD AS A TEMPLATE.
Use the CLC730013 and CLC730027 evaluation
boards for the DIP and SOIC respectively. These board
layouts were optimized to produce the typical perfor-
mance of the CLC405 shown in the data sheet. To
reduce parasitic capacitances, the ground plane was
removed near pins 2, 3, and 6. To reduce series induc-
tance, trace lengths of components and nodes were
minimized.
Parasitics on traces degrade performance. Minimize
coupling from traces to both power and ground planes.
Use low inductive resistors for leaded components.
Do not use dip sockets for the CLC405 DIP amplifiers.
These sockets can peak the frequency domain
response or create overshoot in the time domain
response.
Use flush-mount socket pins when socket-
ing is necessary.
The 730013 circuit board device
holes are sized for Cambion P/N 450-2598 socket pins
or their functional equivalent.
Insert the back matching resistor (R
shown in Figure
2 when driving coaxial cable or a capacitive load. Use
the plot in the typical performance section labeled
“Settling Time vs. Capacitive Load” to determine the
optimum resistor value for
R
out
for different capacitive
loads.This optimal resistance improves settling tim for
pulse-type applications and increases stability.
Figure 2
Use power-supply bypassing capacitors when operat-
ing this amplifier. Choose quality 0.1
μ
F ceramics for C
1
and C
2
. Choose quality 6.8
μ
F tantalum capacitors for
C
3
and C
4
. Place the 0.1
μ
F capacitors within 0.1 inch-
es from the power pins. Place the 6.8
μ
F capacitors
within 3/4 inches from the power pins.
Video Performance vs. I
EX
Improve the video performance of the CLC405 by
drawing extra current from the amplifier output stage.
Using a single external resistor as shown in Figure 3,
you can adjust the differential phase.
mance vs.I
EX
is illustrated below in Graph 1. This graph
represents positive video performance with negative
synchronization pulses.
Video perfor-
Graph1
Figure 3
The value for R
pd
in Figure 3 is determined by :
at +5V supplies.
Wideband Digital PGA
As shown on the front page, the CLC405 is easily con-
figured as a digitally controlled programmable gain
amplifier. Make a PGA by configuring several amplifiers
at required gains. Keep R
f
near 348
and change R
g
for each different gain. Use a TTL decoder that has
enough outputs to control the selection of different gains
and the buffer stage. Connect the buffer stage like the
buffer of the front page. The buffer isolates each gain
stage from the load and can produce a gain of zero for
a gain selection of zero. Use of an inverter (7404) on the
buffer disable pin to keep the buffer operational at all
gains except zero. Or float the buffer disable pin for a
continuous enable state.
Differential Gain & Phase vs. I
EX
D
I
EX
in mA
0.25
0.20
0.15
0.10
0.05
0
2
0
4
6
8
10
D
0.25
0.20
0.15
0.10
0.05
0
Phase
Gain
12
14
16
18
SMA
Output
SMA
Input
R
in
50
R
f
348
R
out
50
3
7
6
4
2
+5V
+
-5V
+
CLC405
+
-
R
g
348
C
1
0.1
μ
fd
C
2
0.1
μ
fd
C
3
6.8
μ
fd
C
4
6.8
μ
fd
R
pull
down
R
f
R
out
+
CLC405
-
R
g
V
in
-V
cc
R
t
V
out
Extra I
-5V
+5V
R
5
I
pd
EX
=
5
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