
CLC405 Typical Performance Characteristics
(A
V
= +2,R
f
= 348
:V
cc
= + 5V,R
L
= 100
unless specified)
I
BI
, I
BN
, V
IO
vs. Temperature
O
I
-60
-20
140
Temperature (
o
C)
V
IO
4.0
3.0
2.0
1.0
0
-1.0
I
B
,
B
μ
A
1.0
0
-1.0
-2.0
-3.0
-4.0
20
60
100
I
BI
I
BN
CLC405 OPERATION
Feedback Resistor
The feedback resistor, R
f
, determines the loop gain and
frequency response for a current feedback amplifier.
Unless otherwise stated, the performance plots and data
sheet specify CLC405 operation with R
f
of 348
at a
gain of +2V/V. Optimize frequency response for different
gains by changing R
f
. Decrease R
f
to peak frequency
response and extend bandwidth. Increase R
f
to roll off
of the frequency response and decrease bandwidth. Use
a 2k
R
f
for unity gain, voltage follower circuits.
Use application note OA-13 to optimize your R
f
selec-
tion. The equations in this note are a good starting
point for selecting R
f
. The value for the inverting input
impedance for OA-13 is approximately 182
.
Enable/Disable Operation Using ±5V Supplies
The CLC405 has a TTL & CMOS logic compatible
disable function.
Apply a logic low (i.e. < 0.8V) to pin
8, and the CLC405 is guaranteed disabled across its
temperature range. Apply a logic high to pin 8, (i.e. >
2.0V) and the CLC405 is guaranteed enabled. Voltage,
not current, at pin 8 determines the enable/disable
state of the CLC405.
Disable the CLC405 and its inputs and output become
high impedances. While disabled, the CLC405’s
quiescent power drops to 8mW.
Use the CLC405’s disable to create analog switches or
multiplexers.Implement a single analog switch with one
CLC405 positioned between an input and output.
Create an analog multiplexer with several CLC405s.
Tie the outputs together and put a different signal on
each CLC405 input.
Operate the CLC405 without connecting pin 8.
internal 20k
pull-up resistor guarantees the CLC405
is enabled when pin 8 is floating.
An
Enable/Disable Operation for Single or
Unbalanced Supply Operation
Figure 1
Figure 1 illustrates the internal enable/disable opera-
tion of the CLC405. When pin 8 is left floating or is tied
to +V
cc
, Q1 is on and pulls tail current through the
CLC405 bias circuitry.
When pin 8 is less than
0.8V above the supply midpoint, Q1 stops tail current
from flowing in the CLC405 circuitry. The CLC405 is
now disabled.
Disable Limitations
The feedback resistor, R
f
, limits off isolation in inverting
gain configurations. Do not apply voltages greater than
+V
cc
or less than -V
ee
to pin 8 or any other pin.
Small Signal Pulse Response
O
Time (5ns/div)
0.20
0.10
-0.10
-0.20
0.00
A
V
-1
A
V
+1
Large Signal Pulse Response
O
Time (5ns/div)
2.0
1.0
-1.0
-2.0
0.0
A
V
-2
A
V
+2
Settling Time vs. Capacitive Load
S
s
(
10
100
1000
CL (pF)
C
L
1k
R
s
+
CLC405
-
348
348
V
o
= 2V step
T
s
R
s
50
40
30
20
10
0
R
s
)
100
80
60
40
20
0
Short Term Settling Time
V
o
Time (ns)
0.2
0.1
-0.1
-0.2
0.0
0
20
100
80
60
40
V
out
= 2Vstep
PSRR and CMRR
P
10k
100k
1M
Frequency (Hz)
10M
100M
60
50
40
30
20
10
PSRR
CMRR
20k
20k
Pin 8
Disable
Q
2
Q
1
Pin 4
-V
ee
20k
Bias
Circuitry
I Tail
Supply
Mid-Point
Pull-up
Resistor
Pin 7
+V
cc
CLC405
NOTE: Pins 4, 7, 8 are external
V
cc
-V
ee
2
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